############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC=AE14;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin LOC=D6;
Net sys_rst_pin PULLUP;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;
NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP";
NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP";
NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP";
TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS  TIG;
Net fpga_0_SRAM_CLOCK LOC=AF7;
Net fpga_0_SRAM_CLOCK SLEW = FAST;
Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_CLOCK DRIVE = 16;

## IO Devices constraints

#### Module RS232_Uart constraints

Net fpga_0_RS232_Uart_RX_pin LOC=W2;
Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_Uart_TX_pin LOC=W1;
Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;

#### Module LEDs_4Bit constraints

Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;

#### Module LEDs_Positions constraints

Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;

#### Module Push_Buttons_Position constraints

Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> LOC=B6;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> PULLUP;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> SLEW = SLOW;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> DRIVE = 2;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> TIG;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> LOC=E9;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> PULLUP;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> SLEW = SLOW;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> DRIVE = 2;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> TIG;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> LOC=A6;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> PULLUP;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> SLEW = SLOW;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> DRIVE = 2;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> TIG;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> LOC=F10;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> PULLUP;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> SLEW = SLOW;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> DRIVE = 2;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> TIG;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> LOC=E7;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> PULLUP;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> SLEW = SLOW;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> DRIVE = 2;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> TIG;

Net fpga_0_LCD_GPIO_IO_pin<0>  LOC=AE13;
Net fpga_0_LCD_GPIO_IO_pin<0>  IOSTANDARD = LVCMOS33;
Net fpga_0_LCD_GPIO_IO_pin<0>  TIG;
Net fpga_0_LCD_GPIO_IO_pin<1>  LOC=AC17;
Net fpga_0_LCD_GPIO_IO_pin<1>  IOSTANDARD = LVCMOS33;
Net fpga_0_LCD_GPIO_IO_pin<1>  TIG;
Net fpga_0_LCD_GPIO_IO_pin<2>  LOC=AB17;
Net fpga_0_LCD_GPIO_IO_pin<2>  IOSTANDARD = LVCMOS33;
Net fpga_0_LCD_GPIO_IO_pin<2>  TIG;
Net fpga_0_LCD_GPIO_IO_pin<3>  LOC=AF12;
Net fpga_0_LCD_GPIO_IO_pin<3>  IOSTANDARD = LVCMOS33;
Net fpga_0_LCD_GPIO_IO_pin<3>  TIG;
Net fpga_0_LCD_GPIO_IO_pin<4>  LOC=AE12;
Net fpga_0_LCD_GPIO_IO_pin<4>  IOSTANDARD = LVCMOS33;
Net fpga_0_LCD_GPIO_IO_pin<4>  TIG;
Net fpga_0_LCD_GPIO_IO_pin<5>  LOC=AC10;
Net fpga_0_LCD_GPIO_IO_pin<5>  IOSTANDARD = LVCMOS33;
Net fpga_0_LCD_GPIO_IO_pin<5>  TIG;
Net fpga_0_LCD_GPIO_IO_pin<6>  LOC=AB10;
Net fpga_0_LCD_GPIO_IO_pin<6>  IOSTANDARD = LVCMOS33;
Net fpga_0_LCD_GPIO_IO_pin<6>  TIG;

#### Module DDR_SDRAM constraints

Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=C26;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=E17;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=D18;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=C19;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=F17;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=B18;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=B20;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=C20;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=D20;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=C21;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=A18;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=B21;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=A24;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=B12;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=A16;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=F23;
Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=G22;
Net fpga_0_DDR_SDRAM_DDR_CE_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=G21;
Net fpga_0_DDR_SDRAM_DDR_CS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=F24;
Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=A23;
Net fpga_0_DDR_SDRAM_DDR_WE_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=G19;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=G24;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> LOC=G20;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> LOC=C22;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQS<0> LOC=D25;
Net fpga_0_DDR_SDRAM_DDR_DQS<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQS<1> LOC=G18;
Net fpga_0_DDR_SDRAM_DDR_DQS<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQS<2> LOC=G17;
Net fpga_0_DDR_SDRAM_DDR_DQS<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQS<3> LOC=D26;
Net fpga_0_DDR_SDRAM_DDR_DQS<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<0> LOC=H20;
Net fpga_0_DDR_SDRAM_DDR_DQ<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<1> LOC=E23;
Net fpga_0_DDR_SDRAM_DDR_DQ<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<2> LOC=H26;
Net fpga_0_DDR_SDRAM_DDR_DQ<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<3> LOC=H22;
Net fpga_0_DDR_SDRAM_DDR_DQ<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<4> LOC=E25;
Net fpga_0_DDR_SDRAM_DDR_DQ<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<5> LOC=E26;
Net fpga_0_DDR_SDRAM_DDR_DQ<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<6> LOC=F26;
Net fpga_0_DDR_SDRAM_DDR_DQ<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<7> LOC=E24;
Net fpga_0_DDR_SDRAM_DDR_DQ<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<8> LOC=E20;
Net fpga_0_DDR_SDRAM_DDR_DQ<8> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<9> LOC=A22;
Net fpga_0_DDR_SDRAM_DDR_DQ<9> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<10> LOC=C23;
Net fpga_0_DDR_SDRAM_DDR_DQ<10> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<11> LOC=C24;
Net fpga_0_DDR_SDRAM_DDR_DQ<11> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<12> LOC=A20;
Net fpga_0_DDR_SDRAM_DDR_DQ<12> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<13> LOC=A21;
Net fpga_0_DDR_SDRAM_DDR_DQ<13> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<14> LOC=D24;
Net fpga_0_DDR_SDRAM_DDR_DQ<14> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<15> LOC=E18;
Net fpga_0_DDR_SDRAM_DDR_DQ<15> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<16> LOC=F18;
Net fpga_0_DDR_SDRAM_DDR_DQ<16> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<17> LOC=A19;
Net fpga_0_DDR_SDRAM_DDR_DQ<17> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<18> LOC=F19;
Net fpga_0_DDR_SDRAM_DDR_DQ<18> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<19> LOC=B23;
Net fpga_0_DDR_SDRAM_DDR_DQ<19> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<20> LOC=E21;
Net fpga_0_DDR_SDRAM_DDR_DQ<20> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<21> LOC=D22;
Net fpga_0_DDR_SDRAM_DDR_DQ<21> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<22> LOC=D23;
Net fpga_0_DDR_SDRAM_DDR_DQ<22> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<23> LOC=B24;
Net fpga_0_DDR_SDRAM_DDR_DQ<23> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<24> LOC=E22;
Net fpga_0_DDR_SDRAM_DDR_DQ<24> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<25> LOC=F20;
Net fpga_0_DDR_SDRAM_DDR_DQ<25> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<26> LOC=H23;
Net fpga_0_DDR_SDRAM_DDR_DQ<26> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<27> LOC=G25;
Net fpga_0_DDR_SDRAM_DDR_DQ<27> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<28> LOC=G26;
Net fpga_0_DDR_SDRAM_DDR_DQ<28> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<29> LOC=H25;
Net fpga_0_DDR_SDRAM_DDR_DQ<29> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<30> LOC=H24;
Net fpga_0_DDR_SDRAM_DDR_DQ<30> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<31> LOC=H21;
Net fpga_0_DDR_SDRAM_DDR_DQ<31> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=A10;
Net fpga_0_DDR_SDRAM_DDR_Clk_pin IOSTANDARD = DIFF_SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=B10;
Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin IOSTANDARD = DIFF_SSTL2_II;

#### Module SRAM constraints

Net fpga_0_SRAM_Mem_A_pin<29> LOC=Y1;
Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<28> LOC=Y2;
Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<27> LOC=AA1;
Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<26> LOC=AB1;
Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<25> LOC=AB2;
Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<24> LOC=AC1;
Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<23> LOC=AC2;
Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<22> LOC=AD1;
Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<21> LOC=AD2;
Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<20> LOC=AE3;
Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<19> LOC=AF3;
Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<18> LOC=W3;
Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<17> LOC=W6;
Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<16> LOC=W5;
Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<15> LOC=AA3;
Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<14> LOC=AA4;
Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<13> LOC=AB3;
Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<12> LOC=AB4;
Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<11> LOC=AC4;
Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<10> LOC=AB5;
Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<9> LOC=AC5;
Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8;
Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=Y6;
Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_BEN_pin<3> SLEW = FAST;
Net fpga_0_SRAM_Mem_BEN_pin<3> DRIVE = 8;
Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=Y5;
Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_BEN_pin<2> SLEW = FAST;
Net fpga_0_SRAM_Mem_BEN_pin<2> DRIVE = 8;
Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=Y4;
Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_BEN_pin<1> SLEW = FAST;
Net fpga_0_SRAM_Mem_BEN_pin<1> DRIVE = 8;
Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=Y3;
Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_BEN_pin<0> SLEW = FAST;
Net fpga_0_SRAM_Mem_BEN_pin<0> DRIVE = 8;
Net fpga_0_SRAM_Mem_WEN_pin LOC=AB6;
Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST;
Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 8;
Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=AD13;
Net fpga_0_SRAM_Mem_DQ_pin<31> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<31> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=AC13;
Net fpga_0_SRAM_Mem_DQ_pin<30> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<30> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=AC15;
Net fpga_0_SRAM_Mem_DQ_pin<29> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<29> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=AC16;
Net fpga_0_SRAM_Mem_DQ_pin<28> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<28> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=AA11;
Net fpga_0_SRAM_Mem_DQ_pin<27> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<27> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=AA12;
Net fpga_0_SRAM_Mem_DQ_pin<26> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<26> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=AD14;
Net fpga_0_SRAM_Mem_DQ_pin<25> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<25> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=AC14;
Net fpga_0_SRAM_Mem_DQ_pin<24> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<24> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=AA13;
Net fpga_0_SRAM_Mem_DQ_pin<23> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<23> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=AB13;
Net fpga_0_SRAM_Mem_DQ_pin<22> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<22> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=AA15;
Net fpga_0_SRAM_Mem_DQ_pin<21> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<21> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=AA16;
Net fpga_0_SRAM_Mem_DQ_pin<20> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<20> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=AC11;
Net fpga_0_SRAM_Mem_DQ_pin<19> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<19> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=AC12;
Net fpga_0_SRAM_Mem_DQ_pin<18> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<18> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=AB14;
Net fpga_0_SRAM_Mem_DQ_pin<17> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<17> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=AA14;
Net fpga_0_SRAM_Mem_DQ_pin<16> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<16> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=D12;
Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=E13;
Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=C16;
Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=D16;
Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=D11;
Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=C11;
Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=E14;
Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=D15;
Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=D13;
Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=D14;
Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=F15;
Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=F16;
Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=F11;
Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=F12;
Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=F13;
Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=F14;
Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12;
Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=AC6;
Net fpga_0_SRAM_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_OEN_pin<0> SLEW = FAST;
Net fpga_0_SRAM_Mem_OEN_pin<0> DRIVE = 8;
Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=V7;
Net fpga_0_SRAM_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_CEN_pin<0> SLEW = FAST;
Net fpga_0_SRAM_Mem_CEN_pin<0> DRIVE = 8;
Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=W4;
Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SRAM_Mem_ADV_LDN_pin SLEW = FAST;
Net fpga_0_SRAM_Mem_ADV_LDN_pin DRIVE = 8;


Net fpga_0_LEDs_32ABit_GPIO_IO_pin<0> LOC=Y18;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<1> LOC=AA18;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<2> LOC=W19;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<3> LOC=Y19;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<4> LOC=Y21;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<5> LOC=Y20;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<6> LOC=W24;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<7> LOC=W23;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<8> LOC=Y23;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<8> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<9> LOC=Y22;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<9> IOSTANDARD = LVCMOS33;


Net fpga_0_LEDs_32ABit_GPIO_IO_pin<10> LOC=AA20;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<10> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<11> LOC=AA19;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<11> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<12> LOC=AA17;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<12> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<13> LOC=Y17;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<13> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<14> LOC=AC20;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<14> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<15> LOC=AB20;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<15> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<16> LOC=AD21;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<16> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<17> LOC=AE21;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<17> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<18> LOC=AD20;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<18> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<19> LOC=AE20;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<19> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<20> LOC=AC19;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<20> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<21> LOC=AD19;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<21> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<22> LOC=AB18;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<22> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<23> LOC=AC18;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<23> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<24> LOC=AE23;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<24> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<25> LOC=AF23;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<25> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<26> LOC=AF22;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<26> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<27> LOC=AF21;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<27> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<28> LOC=AF20;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<28> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<29> LOC=AF19;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<29> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<30> LOC=AE18;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<30> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32ABit_GPIO_IO_pin<31> LOC=AF18;
Net fpga_0_LEDs_32ABit_GPIO_IO_pin<31> IOSTANDARD = LVCMOS33;



#Segundo columna de leds, lo asignamos a otra direccion pero se puede colocar
#en el mismo que los de arriba solo que en el chanel 2.

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<0> LOC=AA24;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<0> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<1> LOC=V20;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<1> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<2> LOC=AC25;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<2> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<3> LOC=AC24;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<3> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<4> LOC=W25;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<4> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<5> LOC=AB24;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<5> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<6> LOC=Y24;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<6> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<7> LOC=AB23;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<7> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<8> LOC=W26;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<8> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<9> LOC=Y26;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<9> IOSTANDARD = LVCMOS33;


Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<10> LOC=Y25;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<10> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<11> LOC=AA26;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<11> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<12> LOC=AA23;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<12> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<13> LOC=AC21;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<13> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<14> LOC=AB26;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<14> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<15> LOC=AC23;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<15> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<16> LOC=AB25;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<16> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<17> LOC=AD23;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<17> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<18> LOC=AC26;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<18> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<19> LOC=AD26;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<19> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<20> LOC=AC22;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<20> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<21> LOC=V22;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<21> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<22> LOC=V21;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<22> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<23> LOC=W22;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<23> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<24> LOC=AD25;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<24> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<25> LOC=AB22;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<25> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<26> LOC=W21;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<26> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<27> LOC=W20;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<27> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<28> LOC=AB21;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<28> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<29> LOC=AD22;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<29> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<30> LOC=AE24;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<30> IOSTANDARD = LVCMOS33;

Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<31> LOC=AF24;
Net fpga_0_LEDs_32BBit_GPIO_IO_PIN<31> IOSTANDARD = LVCMOS33;


Net xps_timer_1_PWM0_pin    LOC = D8;
Net xps_timer_2_Gen_pin     LOC = D7;