Degrees: PhD Electrical Engineering, Georgia Institute of Technology, Atlanta, 2001 MS Electrical Engineering, Sharif University of Technology, Tehran, 1994 BS Electrical Engineering, University of Science & Technology, Tehran, 1992
The objective of Dr. Zarkesh-Ha’s research is to enhance the understanding of the limits of, and to provide innovative techniques for, designing the next generation VLSI systems in nanometer CMOS technology. To accomplish this research goal, he has developed several stochastic models for interconnects, including global wire-length distribution, via blockage, fan-out distribution, interconnect pattern density and adjacency distributions, and layout sensitivity. These stochastic models have enabled us to predict the challenging issues in future VLSI technology nodes not yet developed.
• “Interconnect Opportunities for Gigascale Integration,” IBM Journal of Research and Development, vol. 46, pp. 245-263, May. 2002 • “Estimation of Electromigration-Aggravating Narrow Interconnects,” International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 59-67, September 2007
Dr. Zarkesh-Ha is continuing his research on interconnect predictive models to understand the limitation and opportunities for nanoscale VLSI technology. In his most recent publication coauthored with his student, he discusses the limitation on manufacturing nanoscale interconnect due to the interconnect narrowing effect.
Dr. Zarkesh-Ha won the Kharazmi Award, the most prestigious scientific award in Iran, in 1997. He holds ten patents, is author of a book chapter, and author or co-author of more than 40 peer-reviewed journals and conference papers.
With research interests that include statistical modeling of VLSI systems, high-performance and low-power VLSI systems, innovative biologically inspired computer architectures, and reconfigurable digital/ analog systems, Dr. Zarkesh-Ha currently serves as major advisor to three students and teaches courses in advanced VLSI design. He is a senior member of IEEE and a member of ACM.
He was a senior research engineer at LSI Logic Corp., working on interconnect architecture design for the next ASIC generations, before joining ECE in 2006. He has been an industry liaison with Semiconductor Research Corp. and Microelectronics Advanced Research Corp. since 2001. He has also been serving as a technical committee member of the System Level Interconnect Prediction Workshop and reviewer of several top-ranked journals and conferences, including Science Magazine, IEEE transactions on VLSI systems, and the Design Automation Conference.