Model { Name "adc2dac" Version 5.0 SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes on ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ExecutionOrder off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off PreLoadFcn "coef" Created "Thu Oct 09 14:03:04 2003" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "Administrator" ModifiedDateFormat "%" LastModifiedDate "Wed Nov 26 23:38:21 2003" ModelVersionFormat "1.%" ConfigurationManager "None" SimParamPage "RTW" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeMexFile "ext_comm" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on RTWExpressionDepthLimit 5 SimulationMode "normal" Solver "ode45" SolverMode "Auto" StartTime "0.0" StopTime "0.2" MaxOrder 5 MaxStep "auto" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "auto" RelTol "1e-3" AbsTol "auto" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" LoadExternalInput off ExternalInput "[t, u]" LoadInitialState off InitialState "xInitial" SaveTime on TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput on OutputSaveName "yout" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" Decimation "1" LimitDataPoints on MaxDataPoints "1000" SignalLoggingName "sigsOut" ConsistencyChecking "none" ArrayBoundsChecking "none" AlgebraicLoopMsg "warning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" CheckForMatrixSingularity "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SfunCompatibilityCheckMsg "none" RTWInlineParameters off BlockReductionOpt on BooleanDataType on ConditionallyExecuteInputs on ParameterPooling on OptimizeBlockIOStorage on ZeroCross on AssertionControl "UseLocalSettings" ProdHWDeviceType "Microprocessor" ProdHWWordLengths "8,16,32,32" RTWSystemTargetFile "grt.tlc" RTWTemplateMakefile "grt_default_tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off RTWRetainRTWFile off TLCProfiler off TLCDebug off TLCCoverage off TLCAssertion off RTWOptions "-aEnforceIntegerDowncast=1 -aExtMode=0 -aExtModeTes" "ting=0 -aFoldNonRolledExpr=1 -aForceParamTrailComments=0 -aGenerateComments=1" " -aGenerateReport=0 -aIgnoreCustomStorageClasses=0 -aIncDataTypeInIds=0 -aInc" "HierarchyInIds=0 -aInlineInvariantSignals=0 -aInlinedPrmAccess=\"Literals\" -" "aLocalBlockOutputs=1 -aLogVarNameModifier=\"rt_\" -aMaxRTWIdLen=31 -aPrefixMo" "delToSubsysFcnNames=1 -aRTWVerbose=1 -aRollThreshold=5 -aShowEliminatedStatem" "ents=0" BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType DiscretePulseGenerator PulseType "Sample based" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Inport Port "1" PortDimensions "-1" SampleTime "-1" ShowAdditionalParam off LatchInput off DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Outport Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Reference } Block { BlockType Scope Floating off ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "0" } Block { BlockType "S-Function" FunctionName "system" PortCounts "[]" SFunctionModules "''" } Block { BlockType Sin SineType "Time based" Amplitude "1" Bias "0" Frequency "1" Phase "0" Samples "10" Offset "0" SampleTime "-1" VectorParams1D on } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" RTWSystemCode "Auto" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Terminator } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "adc2dac" Location [558, 154, 1087, 546] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType Reference Name " System Generator" Tag "genX" Ports [] Position [215, 248, 266, 298] ShowName off AttributesFormatString "System\\nGenerator" SourceBlock "xbsIndex_r3/ System Generator" SourceType "Xilinx System Generator" xilinxfamily "Virtex2" part "xc2v2000" speed "-4" package "fg676" synthesis_tool "XST" directory "E:/ProjectosXtreme/XUPLab01/adc2dac" testbench on simulink_period "1/44100" sysclk_period "15" trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off } Block { BlockType Reference Name "ADC1" Ports [1, 1] Position [120, 52, 165, 88] LinkData { BlockName "adc1_d" DialogParameters { period "1/44100" } } SourceBlock "XtremeDSPKit/ADC1" SourceType "XtremeDSP Kit ADC1" } Block { BlockType Reference Name "ADC2" Ports [1, 1] Position [120, 125, 165, 165] LinkData { BlockName "adc2_d" DialogParameters { period "1/44100" } } SourceBlock "XtremeDSPKit/ADC2" SourceType "XtremeDSP Kit ADC2" } Block { BlockType Reference Name "DAC1" Ports [1, 1] Position [270, 126, 315, 164] SourceBlock "XtremeDSPKit/DAC1" SourceType "XtremeDSP Kit DAC1" } Block { BlockType Reference Name "DAC2" Ports [1, 1] Position [270, 51, 315, 89] SourceBlock "XtremeDSPKit/DAC2" SourceType "XtremeDSP Kit DAC2" } Block { BlockType Scope Name "Scope1" Ports [1] Position [365, 54, 395, 86] Location [65, 451, 389, 690] Open off NumInputPorts "1" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" } List { ListType SelectedSignals axes1 "" } SaveName "ScopeData1" DataFormat "StructureWithTime" } Block { BlockType Scope Name "Scope2" Ports [1] Position [380, 129, 410, 161] Location [188, 365, 512, 604] Open off NumInputPorts "1" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" } List { ListType SelectedSignals axes1 "" } SaveName "ScopeData2" DataFormat "StructureWithTime" } Block { BlockType Sin Name "Sine Wave" Position [40, 55, 70, 85] SineType "Time based" Frequency "10000" SampleTime "0" } Block { BlockType Sin Name "Sine Wave1" Position [40, 130, 70, 160] SineType "Time based" Frequency "10000" SampleTime "0" } Line { SrcBlock "ADC2" SrcPort 1 DstBlock "DAC1" DstPort 1 } Line { SrcBlock "Sine Wave1" SrcPort 1 DstBlock "ADC2" DstPort 1 } Line { SrcBlock "ADC1" SrcPort 1 DstBlock "DAC2" DstPort 1 } Line { SrcBlock "Sine Wave" SrcPort 1 DstBlock "ADC1" DstPort 1 } Line { SrcBlock "DAC2" SrcPort 1 DstBlock "Scope1" DstPort 1 } Line { SrcBlock "DAC1" SrcPort 1 DstBlock "Scope2" DstPort 1 } } }