About this Lab

The goal of this first lab is for you to meet Sysgen software and the XtremeDSP kit. Sysgen will allow us to create a system in the Simulink (Matlab) environment, simulate it in the same environment, even mix our system (hardware) with soft blocks and finally create the VHDL files necessaries to download the system in an FPGA. The XtremeDSP kit is basically a board loaded with a Virtex-II FPGA, two Analog to Digital Converters (ADC) and two Digital to Analog Converters (DAC) (figure below), which makes this board the perfect target for almost any signal processing lab. The board also has external memory, a PCI and USB interface and a GUI that will allow us to talk to the board in a graphical way. This lab will not be intensive in explaining the different capabilities of the board and the software, but it will provide a glance on the basic capabilities. We will be building more complex systems, and therefore exploiting more capabilities of hardware and software in later labs.

Block diagram taken from XtremeDSP Development Kit User Guide Issue 7

System requirements

• Matlab R13
• Simulink R13
• Sysgen 3.1
• ISE 5.2 SP3
• ModelSim SE 5.6a
• XtremeDSP Kit board
• FUSE Probe 2.5
• Signal Generator and a 100Mhz Oscilloscope
• We are also assuming the reader is familiar with Simulink and Matlab work environment and ISE tools

System description

We will develop an introductory lab by implementing a "bypass" system between the ADC and the DAC channels. This means that we want to put an input signal in both ADC and get it back through the DAC channels. Some basic signal manipulations (inversion, coding, etc) will also be made just to proof the suitability of the software and hardware. To demonstrate how Sysgen can make the design process faster we will first develop this by directly creating the VHDL code and then creating the same system using Sysgen.

Building the system using from scratch "by hand" using VHDL and ISE tools

Let's create our system using ISE tools. The code we will use explain and modify in this section was taken from the examples designs provided with the XtremeDSP kit. First let's make a little introduction to our board, or should we say boards? The XtremeDSP kit is composed by a mother board (BenONE) and a daughter board (BenADDA). The mother board provides the means of communications (PCI/USB) between a computer host and whatever we will put in the daughter board. We will not touch the mother board in this lab, just the daughter one. The daughter boar has a Virtex-II v80 and a Virtex-II V2000 as well as two DACs and two ADCs. The first FPGA (VC2V80) is used distribute the clock signal produced by the oscillator on board (different speeds are possible, check that XtremeDSP user guide)  to the second FPGA (VC2V2000) and the converters. Is the second FPGA the one that will actually host our system. NOTE that this very simplistic explanation of what is loaded in the boards and its functions is by NO means complete. The reader is encourage to carefully read the board datasheet and documentation provided with the XtremeDSP board as well as the datasheet of the converters, also provided with the XtremeDSP board. The concepts and information shared in this labs is just enough for us to follow and understand the development of the lab. Also NOTE that the XtremeDSP board can be populated with different versions/packages of FPGAs, so be CAREFUL and check which ones are in your board. Make changes to the next steps is necessary.

Since the system will be host by the VC2V2000 FPGA, lets create a new project for it. Go to ISE Project Navigator and create a new project with the configuration shown in figure 1.

Figure 1

The system we will create is described in the block diagram shown in figure 2. A DCM (Digital Clock Manager) blocks provide self-calibrating, fully digital solutions for clock distribution delay compensation, clock multiplication and division, coarse and fine-grained clock phase shifting. The DCM and global clock multiplexer buffers (BUFG and IBUFG) provide a complete solution for designing high-speed clocking schemes [1]. Note that we won't use all the capabilities of the DCM. The PROCESS block is basically a set of registers and provides the conversion between 2's complement (output of the ADCs) to offset binary (DAC's inputs). Additionally, DAC's and ADC's control signals are generated. To complete the example, a pattern is written in the available Leds of the daughter board.

Figure 2

 The VHDL code is provided with by Nallatech with the XtremeDSP kit as a design example, a copy can be downloaded here. Add the VHDL source code to your project and the .ucf file provided here. Note that the .ucf file has a bunch of lines commented. The idea of this file is that we will be able to enable or disable constraints as necessary in future designs, so keep this file nearby. Run the synthesis and create the bit file.

Now we also need to configure the small FPGA (VC2V80) to distribute the clock signals. The program for this FPGA is provided with the XtremeDSP kit for the case of external (the channel in the middle of the daughter board is for being used as an external clock source) and internal oscillators and doesn't really need to be changed. In this case and in the future labs we will keep using the same program since that particular design is not a point of interest for the goals of these labs. Create a new project with the options shown in figure 3, get the code here, run the synthesis and create the bit file.

Figure 3

Now that we have both files lets try it in the board. Note that we are not going to simulation, the reader is encouraged to create testbenches and simulate the design as a practice. Now connect the board to your USB port using the cables provided with the XtremeDSP kit, as shown in figure 4.

Figure 4

To configure the board we will need to meet FUSE Probe software, which is a GUI provided with the XtremeDSP kit. Go ahead and call FUSE. A windows similar to figure 5 should be the result.

  Figure 5

Go to the "Card Control" menu and click in "Open Card" option, you should get a window similar to figure 6. Select USB and click in "Locate Cards" to locate your card (figure 7). Now click in "Open Cards" to get a window as shown in figure 8.

Figure 6

Figure 7

Figure 8

Note the FUSE has detected all the FPGAs in both boards, mother and daughter. In the daughter board, it has detected the two FPGAs we have been taking about. To configure the FPGAs, make a right click on each of them (start with the Virtex 2V200) and select the option "Assign and Configure" as shown in figure 9.

Figure  9

A file browser will open, select the files (adc2dac.bit for the Virtex 2V2000 and osc_clk.bit for the Virtex 2V80) for both FPGAs and click Ok. Now our design is loaded to the board, let's test it!! Setup an oscilloscope and a signal generator as shown in figure 10.

Figure 10

Be careful with the amplitude and frequency of the generated signal. The oscillator in the daughter board has a maximum frequency of 64Mhz. What does it means in terms of the maximum frequency for the input signal (think about the sampling theorem)? Also, since both converters work with fixed point representation (1_13, which means a 14 bits number using 13 for the decimal part), the amplitude of the input signal is also limited. Can you tell what is the maximum amplitude that can be represented? The reader should also check the maximum and minimum input ranges in the datasheets to avoid possible damages to the converters. By now, you should get a result similar to figure 11.

Figure 11

Well, this was kind of easy because the system to implement was simple, which will not always be the case. Lets now see how can be do just the same but using Sysgen.

Building the system using System Generator

By installing Sysgen 3.1 in your computer (details of installation process can be obtained at XtremeDSP site) you are adding a library of block sets to Simulink as shown in figure 12. 

Figure 12

The blocks are classified under basic categories for easy finding. This section, as well as the next labs, will take you through the process of placing one block at a time and explaining to you each process along the way.  You can find all the information on any type of block in one of two places since all the block sets fall into one of two categories.  Here are the two manuals.  The first is from Xilinx and is a pdf file.  The second is from Matlab and is unfortunately a web link.

We wish to make a new model. The larger concept here is that we are going to create a project. This project is going to appear schematically to us. We are then going to simulate the VHDL created by it. By looking at the figure 13, you can see that this VHDL could then be transferred to an existing FPGA or could be combined into a larger design. The latest news release from Xilinx actually shows were a company is creating an entire wireless radio system in this way.

Open a new Simulink sheet and save it as ADC2DAC. Sysgen provides specific blocks that represent the ADC and DAC converters available in the XtremeDSP board. Those blocks will handle all required control signals for the converters as well as data conversion. Drag those symbols into the new Simulink project and add a sinousoidal source as well as a sink, just for the sake of the simulation. By now, it should look like figure 14.

Figure 13. System Generator Design Flow[2]

Figure 14

Set the sinusoidal signals as a Time Based signal, its amplitude to 1 and its frequency to 10000. Make a right click at Xilinx blocks and go to the option "Look under the mask" (figure 15) to see what is inside the blocks.

Figure 15

In the case of the ADC you will see a register, which is kind of obvious and a Xilinx block called "Xilinx Gateway". These Xilinx Gateway are an important part and are required because the software (namely Matlab/Simulink) works with floating point number representations while our hardware system will not. Therefore, in order to be able to run a simulation in this mixed environment we need a way to "translate" the numbers Matlab is working with into numbers our hardware system will understand. That is the role that these "Xilinx Gateways" have. These blocks must always be introduced in the boundaries of our hardware system, for that reason we are provided with input and output gateways. The "translation" of numbers is configurable at those gateways (double click on the gateways symbols to take a look at the options availables).

In the case of the DAC you will see a more complicated system under the mask and that is because the DAC requires control signals to be generated.

In order to run the simulation another token or symbol is needed. In the Simulink library browser go to Xilinx Blockset/ Basic Elements; pick the icon "System Generator" and drag it into you design. This block is the interface for the Xilinx System Generator to generate HDL code for the subsystem hierarchy in which the block resides. Double click in the System Generator icon and setup the properties according to figure 15. All properties are straight forward, if you need more details go to the help button in the same interface.

Figure 16

The important thing here is to configure the product family of the target device as well as the directory where we want to store the vhdl files that Sysgen is going to generate. Make sure the Simulink System Period is the same in this menu as well as in the system's input gateways. Be sure to setup the simulation time to a reasonable value and run the simulation. You will see at the output scope the same signal that was introduced in the system's input. The final Simulink model file can be downloaded from here.

Once we are happy with the results of the simulation we can generate the vhdl code for our system: double click in the system generator token again and click in the Generate button.

Now go to ISE tools and open the project that we just generated (the files should be stored in the directory configured in the system generator token). Note that System Generator also created testbenches (if the option is enable in the system generator token configuration menu). To create the bit file to configure the FPGA we need to add a UCF file. Take the one we use in the first realization of this lab and add it to the system as the constraint file for the top level vhdl file. The UCF file will need some changes:

• First, notice that in this case, system generator declared one bit signals as vectors (std_logic_vector(0 downto 0)). This means that the UCF file needs to be changed accordingly.
• Second, Note that the clock signal in the VHDL file has the name "clk" and in the UCF file has the name OSC_CLK. Change either one or the other.

Now generate the bit file. Some warnings will be generated basically informing of simplifications made by the compiler and non connected signals. The final ISE project files can be downloaded from here.

Download the bit file to the board in the same way we did before. Don't forget to also download the osc_clk.bit file for the 2VC80 FPGA. Connect the signal generator and the oscilloscope; voila!, we got the same result as before.

Conclusion

Although in this case the system generator way seemed to be more complex, for more complex system this way of working is extremely faster than vhdl coding from scratch. To prove it, try the following:

Change the Simulink project and add an inverter to it. Generate the vhdl files, the bit file and tested it.

Change again the Simulink project and now add an Adder and a Subtract block to the system. Put the sum of the input signals in one DAC and the difference in the other. Generate the VHDL files, the bit file and test it.

How long did it take you to do the changes? Now try to do the same by vhdl coding. Depending on how good are you at it, it will probably still be very similar the amount of time and effort.

The next labs will definitely prove how useful System generator can be.

References

[1] Virtex II Platform FPGAs: Complete Data sheet (ds031.pdf)

[2] http://www.xilinx.com/ipcenter/dsp/ref_guide.pdf