Computer Logic Design Lab

• Later on, you need to record your labs in your lab notebook. The notebook must contain, VHDL source code, test bench, UCF file, output waveforms and RTL view of your design.
• Please read the Lab Notebook Requirements for more inforemation.
• By Anthony: Download/install tutorial for ISE and ModelSim
• Please make sure to delete all your project files from the computer before you leave. Otherwise if someone else use your code both you and the one that used your code would be responsible.

Date due (1/30/2012 - 2/3/2012) in your lab time.
Lab 1 Part 1: Introduction to VHDL, ISE and ModelSim.

• Lab Manual Part 1/Tutorials
• Files for part 1: Source file , Testbench file and UCF file

Lab 1 Part 2: Basic VHDL language constructs. Concurrent signal assignment statements, components. READ RTL BOOK SECTION 2, UP TO SUBSECTION 2.2 (included), and SECTION 3, UP TO SUBSECTION 3.2.3 (included).

• Lab Manual Part 2/Tutorial
• Lecture notes: lecture 1 , lecture 2
• Files: The source code is at the end of the Tutorial
• Worksheet

Date due (2/6/2012 - 2/10/2012) in your lab time.
Sequential statements of VHDL. Process. Use of variables in sequential circuit description. Counters. READ RTL BOOK SUBSECTIONS 3.3 AND 3.5, SECTION 4 UP TO SUBSECTION 4.4 (included), SECTION 5 UP TO SUBSECTION 5.5 (included)

• Laboratory Manual/Tutorial
• Worksheet
• Lecture notes - slides
• Files: The source code is at the end of the Tutorial
• Extra features if interested
  • If we want to have a six bit couner,what changes is needed in VHDL and UCF file. Try it.
  • Use SW#1 and SW#2 to increase/decrease the speade of timer. Try to implement it.

• Date due (2/13/2012 - 2/17/2012) in your lab time.
• Laboratory Manual/Tutorial
• Worksheet

• Date due (2/20/2012 - 2/24/2012) in your lab time.
• Catch up time - we wont have new lab this week.
• Please complete all the labs/worksheet parts that you havent completed yet.

• Date due (2/27/2012 - 3/2/2012) in your lab time.
• Date due (2/27/2012 - 3/9/2012) in your lab time.
• Laboratory Manual/Tutorial
• Lecture
• Later on, you need to record your labs in your lab notebook. Please read the top part of this page for some detail on Lab Notebook Requirements.

• Date due (03/19/2012-03/30/2012) in your lab time.
• Laboratory Manual/Tutorial (ppt)(pdf)
• Worksheet (pdf)
• Please make sure to delete all your project files from the computer before you leave. Otherwise if someone else use your code both you and the one that used your code would be responsible.
• How to debounce manual clock: http://www.cosmiac.org/debounce.html

• Date due (04/3/2012-04/13/2012) in your lab time.
• Date due (04/3/2012-04/20/2012) in your lab time.
• In this lab You are supposed to implement part 18.1 of your textbook.
• Laboratory Manual and worksheet (pdf)

• Date due (04/232012-04/27/2012) in your lab time.
• In this lab, you are supposed to implement part 18.2 of your textbook.
• 1. Read 18.2 part of your book catrefully.
• 2. Most of the code it written for you. Download these files and add them to a blank project.
  • Multiplier.vhd
  • Multiplicand.vhd
  • FourBitAdder.vhd
  • ACC.vhd
  • ParallelMultiplier.vhd
  • ParallelMultiplier_TB.vhd
• 3. The main missing part is the state machine in ParallelMultiplier.vhd file, testbenches and UCF file. Study the above code and modify them appropriately.

Information on how to use ISE:

• Spartan-3E Starter Kit Board User Guide
• How to install Xilinx's software
• ISE 10.1 Quick Start Tutorial
• ISE 11.5 Quick Start Tutorial
• ISE - 13.3 Tutorials
• ISE In-Depth Tutorial
• Xilinx ISE WebPACK VHDL Tutorial

Misc:

• Chips information
• Wiki Page for VHDL manage by ECE Department UNM
• Using Digital Clock Managers in Spantan-3 FPGAs
• COSMIAC UNM