Objectives:

1. To design circuits through the use of truth tables and K-maps.
2. Familiarization with designing and testing (through the use of truth tables) circuits using silicon chips.
3. To use ISE 5.2i to create a circuit and simulate it.
4. Explore K-Map reduction software.

For completion of this lab you will need to read and understand the Lab assignment. The overall plan is to develop a knowledge for determining what the assignment calls for. All logic will then be developed on paper. For most of the first labs, there are two parts: the physical part with 7400 chips and the Xilinx part. A Lab Report will then be required from all students. Go to Lab Report Layout for more information on lab report formats.

The creation of the Xilinx portions of the lab will take time in the beginning. As with any new software package, learning the ins and outs takes time and practice. The ISE Sample Project from ISE Lab Introduction should help explain the necessary steps to get through Lab 1.

For Part 1, the code and testbench code are given. Consequently, it is just a matter of following the procedures outlined in ISE Sample Project including the simulation. Part 2 is a little bit more challenging because the code is not included, but with the example code given so far, it should be easy enough to figure out.

Part 1: Create a 2-Input NAND from a 3-Input NAND

The worksheet contains a truth table for the NAND functions (A*B)', (A*B*0)', and (A*B*1)'. Fill out the entire truth table. Based on what the results are, implement a 2-input NAND gate using a 3-input NAND gate.
A. Design the circuit on paper using a 3-input NAND gate. The inputs are A and B. The output is F = (A*B)'.
B. Draw a logic diagram.
C. Draw a layout diagram giving the relative position of the chips on the breadboard.
D. Develop the F = (A * B) circuit in Xilinx. Using ISE Sample Project as your guide, paste the VHDL Code and the testbench code (found below) into a newly created project.
E. Compare your simulation to your truth table.


NAND CODE

--*********************************************
-- File: Lab1_1.vhd
--
-- Purpose: This file is used to introduce students to the
-- functions of the NAND gate. It uses two inputs and
-- one output.
--
-- Created: 8/1/02 TB
-- Modified: 8/1/02 TB
--Fixed comments
--
--*********************************************
--Defining the library packages to be used

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Declaration of the module's inputs and outputs
--The modules name is "nand"

entity Lab1_1 is port (

A: in std_logic;
B: in std_logic;
Y: out std_logic

);
end Lab1_1;

--Defining, descriptively, the modules internal structure or behavior
architecture behavioral of Lab1_1 is
begin
fcn: process (A, B) begin

Y <= A NAND B;

end process;
end behavioral;


NAND TEST BENCH CODE

--*********************************************
-- File: Lab1_1_tb.vhd
--
-- Purpose: This file is used to test the Lab1_1 VHDL code.
-- It uses three inputs and one output.
--
-- Created: 8/1/02 CK JH TB
-- Modified: 8/15/02 TB
-- Fixed comments
--
--*********************************************
--Defining the library packages to be used
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

--Declaration of ModelSim libraries use
--INTERNET STUDENTS ***using Modelsim XE comment out the next two lines.
--Regular lab students leave them as is.

LIBRARY UNISIM;
LIBRARY XILINXCORELIB;

ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS

COMPONENT Lab1_1
PORT (

a : in std_logic;
b : in std_logic;
y : out std_logic

);
END COMPONENT;

SIGNAL a : std_logic;
SIGNAL b : std_logic;
SIGNAL y : std_logic;

--Defining the variable "CLK_PERIOD" to be equal to 20 nano seconds
constant CLK_PERIOD : time:= 20 ns;

BEGIN
--Unit under test is the module nand. Notice that it is not case sensitive
UUT : Lab1_1
--Defining external interface signals. This associates ports of the named entity with
--signals in the current architecture.
PORT MAP (

a => a,
b => b,
y => y

);

--Three separate processes that provide for the three separate and distinct inputs.
--All three processes will run at the same time. A process is a collection of "sequential" --statements executing in parallel with other concurrent statements or processes Clock --for A
CLOCK: process
begin

a <= '0';
wait for CLK_PERIOD/2;
a <= '1';
wait for CLK_PERIOD/2;

end process;

--Clock for B
CLOCK2: process
begin

b <= '0';
wait for CLK_PERIOD;
b <= '1';
wait for CLK_PERIOD;

end process;

END testbench_arch;


Internet students use Winbreadboard to construct and simulate the circuit. Regular students build the circuit on the logic trainer in the lab and demonstrate the circuit to your TA verifying that the circuit operation agrees with the truth table.


Part 2: A function with four variables

Here is a Boolean function of four variables:

F3=A'B'D + BC'D + A'BC + ACD

A. Fill out the truth table for F3 in the work sheet.
B. Immediately below the truth table for F3 is a K-map. Fill out the K-map.
C. Use it to simplify the Boolean function. Show your work.
D. Design the simplified circuit using any 7400 logic you wish. There are four inputs: A, B, C, and D (along with the complements). There is one output: F3.
E. Draw a logic diagram.
F. Draw a layout diagram giving the relative position of the chips on the breadboard.

Internet students use Winbreadboard to construct and simulate the circuit. Regular students build the circuit on the logic trainer in the lab and demonstrate the circuit to the lab teaching assistant (TA). Verify that the circuit operation agrees with the truth table.


Part 3: Xilinx project implementation.

Implement the simplified F3 from part 2 of this lab using the Xilinx software. The VHDL code for both the project and the testbench will need to be writen. The test bench will have to be sufficient enough to verify that the code is working properly


Part 4. K-Map Software

There are several software packages available that help with K-Map minimization. One such package should be available as an icon on the desktop of this computer. It is called KMAP. If there is not an icon on the desktop, use explorer to go to the following directory: c:\kmap and use the KMAP executable. This particular package is Karnaugh Map 4.4.5 software. For the price, it is a great little package. A copy of it can be purchased for around $15.00 by clicking here or going to the links page. Take some time to become familiar with the software. The worksheet has some required assignments to be done.


Deliverables for LAB 2

Deliverables are the additional documentation that needs to be handed in along with the Lab Report. For this and all following labs use Lab Report Layout as your guide. In this lab include the following deliverables in your report to the TA:

1. A printed copy of the VHDL Code and the testbench code from Part 3.
2. A printed simulation waveform datasheet for Part 3 (enough of the waveform so that all sixteen possible input combinations are shown). To do this use the Print Screen key on your keyboard and paste it into a Word document.
3. The worksheet
   
   
   Click here to go to Lab 1 Worksheet.