Objectives:

By the time the student has completed this lab and it's associated tutorial, the student should be familiar with the following:

1. Using multiplexers in circuit design.
2. Using the Xilinx ISE software and ModelSim to create and verify the
   operation of a simple digital arithmetic design.
3. Using the Xilinx CORE Generator System to create designs in the Xilinx
   ISE design suite, and simulate them using ModelSim.

Part 1: Multiplexers

Here, you will be using multiplexers to implement a basic subtractor circuit. The multiplexer you will be using is the 8-to-1 multiplexer. You will need to decide how to best set up the control lines and inputs to derive the correct results. It is suggested you use the following design process:

A. Design the circuit on paper.

1. Fill out K-maps for subtractor. Remember that it has three inputs:
   X, Y, and B_IN, and two outputs: D, and B_out. This means you
   will need two K-maps.
2. Design this circuit using the 8-to-1 multiplexers. Look at your
   K-maps and decide how to best setup the control lines, and the
   eight input lines to generate the two correct outputs.
3. Draw the logic diagram for the subtractor. This will give you some
   idea of how much board space you will save when you implement
   the design using multiplexers, rather than basic logic gates.

B. Implement your design on the prototyping boards in the lab. Debug your design and then demonstrate it to your TA.

Part 2: Using Xilinx.

Here, you will take the circuit you designed in Part 1, and implement it using the Xilinx ISE design suite. Recall that the tutorial has shown you how to do this. Multiplexers are represented in VHDL by case-statements. In the 4-to-1 multiplexer example in the tutorial, that meant that we had a case statement with four possible valid results, looking like this:

case XY_IN is
when "00" => DIV_OUT <= BROW_IN;

Successfully completing the first half of the tutorial will be sufficient introduction for this part.

Part 3: Using The CORE Generator System.

For this part of the lab, you will be working exclusively in the ISE design suite. Using the second part of the tutorial as your guide, create an ISE project with the CORE Generator System.

Create an 8-bit Registered Adder core for Spartan2E. You will then need to write the VHDL top-level source file and the VHDL testbench to simulate it in ModelSim.

We will supply you with portions of the testbench. However, you will be expected to write much of it on your own.

When writing your testbench, you should at least have the following:

-Add two small positive numbers together (say 00000110 and 00000001).
-Add a positive number (00000010) and a negative number (11111110).
-Add this number (011111111) and (00000001). What happens?

Below is the basic framework of your testbench:


LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

--Declaration of ModelSim libraries used
LIBRARY UNISIM;
LIBRARY XILINXCORELIB;

ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS
-- This is the one of the components we will be simulating.
-- You will supply the necessary component declaration here.

-- Here, we will be adding some signals.
SIGNAL a_data_in : std_logic_VECTOR(7 downto 0);
SIGNAL b_data_in : std_logic_VECTOR(7 downto 0);
SIGNAL clock_in : std_logic;
SIGNAL carry_in : std_logic;
SIGNAL sum_data_out : std_logic_VECTOR(7 downto 0);

-- Next, I will define a standard clock of 40 ns, or 25 MHz
-- (When you actually configure the FPGA and CPLD boards,
-- they have a minimum clock time of about this.)
--Defining the variable "CLK_PERIOD" to be
--equal to 20 nano seconds
constant CLK_PERIOD : time:= 40 ns;

BEGIN
-- Unit under test is the module complement. Notice
-- that it is not case sensitive. Here you will have the component
-- that you declared above. Except in the port map, you will assign
-- the ports to the simulation signals I defined above.

-- Now I will define some of the basic processes. I'm taking the easy ones.

master_clock : PROCESS
BEGIN
clock_in <= '0';
wait for CLK_PERIOD / 2;
clock_in <= '1';
wait for CLK_PERIOD / 2;
END PROCESS;

carry_in_forever : PROCESS
BEGIN
carry_in <= '0';
wait for CLK_PERIOD;
carry_in <= '0';
wait for CLK_PERIOD;
END PROCESS;

-- Here you will supply the appropriate input for the two numbers to add.
-- Let each input combination sit at the appropriate place for a reasonably
-- long time. Start at CLK_PERIOD * 4 and work your way up until the
-- outputs are stable and what you'd expect them to be.

END testbench_arch;


Once you have written and simulated the testbench, answer the following question:

Why is the SUM output one bit larger than either the A or B inputs?

When you have completed the lab, turn in the following with your report:


1. What was asked of you from the tutorial.

2. A printed copy of your VHDL project, including the top-level file, your
completed VHDL testbench, and a printout of your ModelSim simulation
for parts 2 and 3.