This tutorial highlights the initial steps of creating a project on programmable logic. The main difference between this lab and earlier ones is that this lab will not stop with merely simulating the project. The programmable device you will be using is the Coolrunner CPLD. The sequece detector creater here will detect the sequence 10010.

Launch Project Navigator from the desktop or from the Start menu. Go to File, New Project. Make sure the chosen values are the ones listed below. It is essential to choose the correct CPLD part number for the project to work. There are ways to change this part number after creating the project, but it is just easier to get it correct the first time. As for project name, choose whatever name you wish.

Here is where some source code needs to be added. This sequence detector project will use VHDL source code. The code is implemented with three inputs and seven outputs. It has a reset, an input variable called X, and a clock. It has one output called Z, which will go high only when the exact sequence is recognized or detected. Here is the code for the sequence detector. Take the code and copy it and then paste it into your project. Next, here is the code for the test bench. Add it to the project and run the simulation.

There are certain things you should gain from looking at the simulation. First, look for specific output occurrences based on specific inputs. This current simulation says that if the required sequence is accompanied with a low reset and rising clock edges on each instance of the bit, the result will be a high output on Z. It says nothing about what will happen given any other set of inputs. For an exhaustive and complete simulation, you would have to spend a great deal of time actually working through ALL the possible combinations of inputs. This is beyond the scope of this project. It is impossible to say enough about simulation. Every hour you spend on making sure your simulation works and that your device is operating the way you expect pays you hours that you will not spend debugging your projects later. The fact that your simulation works is not a guarantee that your final project will work, but it is an indication that you might be heading the right direction. The intention of this project is to tie three inputs to three switches and seven outputs to seven LEDs.

In the past this is pretty much where we have stopped. At this point you are done with the design tools and are working onto other parts of the software. The rest of the project uses what Xilinx refers to as the back end software. By looking at your VHDL you realize that there are three inputs and seven outputs you have to deal with. Your chip has 44 pins of which you must choose ten. Looking down onto the board, I can tell you that most of the spare pins (some are reserved for power and ground) are hard wired into things like switches and LEDs. This is done to make it easier for us. In later courses you would be wiring those up yourselves. Our problem is that we have to identify which of the switches and which of the LEDs we want to use. I am going to use BTN1 (button one) for my clock, SW2 (switch two) for reset (reset restarts me at my initial state), and SW3 for X. I will use LD1 (LED one) for my state A, LD2 for my state B, and so forth. Finally, I will use LD7 for Z (sequence detected).

My original plan was to use SW1 for my clock but this did not work. The reason it did not work is an excellent aside that you should be aware of. There is a term called debouncing. If you can imagine a ball bouncing between one and zero, that is what happens with some mechanical devices like switches. Even though to you it may seem that you are sliding the switch from zero to one, the delicate circuitry within the CPLD sees this as a series of ones and zeros. These switches are described as dirty due to these characteristics. For our benefit, the buttons on the xcr board are debounced which means that each time we push them, we get exactly one transition from zero to one and then back to zero when we release it.

To solidify my inputs and outputs, I have to edit my user constraints. This means I am going to constrain my project to do what I wish in terms of my inputs and outputs. Make sure you have the main file highlighted (not the testbench). Go to the Project menu. Select New Source. You should be looking at a window like the one below.

Choose Implementation Constraints File, name your file and click Next, Next, Finish. This will create a file with extension .ucf that is now visible in the Sources in Project window. Double click the file. This will launch the constraints editor. Click on the Ports tab.

This will actually be very important in later projects where you will be using 5-10 VHDL files in a single project. As you can see, it shows our three inputs and our seven outputs. This is where we will identify our locations (pins) on our CPLD and tie them to our desired descriptive outputs. This is one of the places where the real beauty of programmable chips begins to shine. If I were to make a mistake and pick the wrong pins, it is easy enough to come back to this spot and make a change. The pinouts for the Digilent board ARE HERE. By opening up this document and looking at the bottom of the last page you will find a chart (table 3) that translates from pin number to function. Here are the desired assignments for my variables.

clk BTN1
reset SW2
x SW3
a1 LED1
b1 LED2
c1 LED3
d1 LED4
e1 LED5
f1 LED6
z LED7

You will need to look up the pin numbers and enter them into the Location field.

Once you have finished entering the pin numbers click the Save button and close the window. This closes the Constraints Editor and brings us back to the project.

Ensure that the project VHDL is highlighted and then double click on the Synthesize circular icon. You may get a notice asking you to reset or return. Choose reset. You are now leaving your test bench behind. Its sole purpose is to help with simulation. Once you double-click on synthesis then the software is going to begin to transform your descriptive language into what is called a netlist. Next you will need to double click on the circle next to Implement Design. Here is a slide from Xilinx that shows you how they interpret what is going on.

You may receive a warning about invalid target architecture. You will know this by seeing a yellow explanation mark on next to exclamation. If you do not, do not worry about it. If you do, scroll up (in the lower section) until you find the warning. You will note that it has a little yellow "web" symbol next to it. If you right click on it and go to solution record it will take you to the Xilinx solutions Internet site. If there is a record of your error or warning, it will identify it and provide you with any additional information. This is a very handy feature for larger projects. Once implementation is complete you will get a green check mark or a yellow exclamation mark next to Implement Design (both are acceptable). Let's go into Implement Design and see some of the results. Click on the "+" to expand Implement Design. Expand Fit and double click on Fitter Report. You will want to print the first couple of pages of this since you will need it for one of your deliverables. Now double click on View Fitted Design. This will lauch ChipViewer. You will need to be patient as this program may take a few minutes to launch. Click on the top view button on the top tool bar.

By looking at the chip above you can see where your three inputs and seven outputs are located. The black dot in the upper center can be seen on the chip as a small dimple above and over the side from the word Xilinx. Please avoid putting your fingers on the chips, as they are extremely electrostatic discharge sensitive. Close chip viewer and return to the main program. Now we will want to double click on the circle next to the Generate Programming File. You should be rewarded with a green check mark. Now we are down to the final steps of actually programming the device. Expand the Generate Programming File section and double click on the Configure Device (iMPACT) icon to launch iMPACT. iMPACT stands for intelligent Multi-purpose Programming And Configuration Tool.

An Operation Mode Selection dialog box will come up. Choose Configure Devices and click Next. Then a Configure Devices dialog box will pop up. Choose Boundary-Scan Mode and click Next. Then a Boundary-Scan Mode Selection dialog box will come up. Choose Automatically connect to cable and identify Boundary-Scan chain and click Finish. Click Ok.

An new window like below will pop up. Browse to the directory of your project and open seq_req.jed (unless you renamed the file).

You will then be in the main iMPACT window. At this point you would want to make sure you have the power to the CPLD board switched on (turn on power strip and make sure black slide switch next to the parallel cable connector is set to EXT) and the A/B switchbox on the top of the computer is set to CPLD.

Click on the Xilinx chip to highlight it. It will turn green.

Then, click on Operations, Program. The following window will appear. Make sure all of the options are the same and click OK.

There is a Read Protect option at the top of the screen. Consider the situation where your customer purchased the finished product but did not purchase the source code or you wished the source code to remain secret. There is a large industry involved in extracting the source code from programmed devices. By checking this block you disable the CPLD design from being read back. It is a read protect option. At the bottom of the screen you will see a block called XPLA UES. UES stands for user electronic signature. You must remember that you are programming this device. After it is done you would remove it and ship it out to the user. Many times as a programmer you might want to leave reminder information within the device. A good idea for me is to leave my name and the date programmed.

Once the device has been successfully programmed you will see the following:

You should be informed that programming succeeded. Another thing to notice here is the fact that you have created and transferred down the *.jed (referred to as "JEDEC") file. You will need one .jed file for each of the devices you need or desire to program. An example would be if you had two or more CPLDs on a single board (not uncommon). Within each CPLD is something called a TAP (test access port) controller. This controller is what is essential for the device to be able to handle ISP (in system programming). What you have done now is communicate through that controller to transfer your program onto the device. Now for the testing of our project.

We start by resetting the board, which means setting the reset high. Pushing switch 2 away from you does this. It will probably be helpful for you to be looking at your state diagram (ModelSim waveform from testbench) and your VHDL while you are testing out the device. What you will notice is that with reset high, no matter how many times you change X or how many clock pulses you give the button, you will stay in state A. Now we are going to set reset to low and begin looking for the sequence. Give X a high by pushing it away from you and then giving the clock (BTN1) a push. You should have stepped to state B with corresponding LD2 being lit. Set X to 0 by pulling SW3 back to you and giving a clock pulse. Continue through your sequence until you see Z (LD7) lit.

As a design engineer you would continue testing your design until you were comfortable that it worked as requested. You could think of the sequence as a series of failures in a device and the corresponding output of LD7 as activation of a warning light. Now reach up and switch the power off and on to the power strip. What you will find out is that the devices programming (and your UES) are stored on the chip. At this point you could remove the device and ship it off (but please do not do so).