--***********************************************************
--File:		Accumulator for Lab 6  accumvhd.vhd
--
--Purpose:	To introduce students to accumulators
--		and their functions.  This project source code
--    was originally taken from toolbox.xilinx.com
--    but was modifed for our purposes.  It has a 
--    four bit input and an eight bit output/accumulator
--		capability.  The inputs will be the four switches
--		from the digilent XLA3 board and the output
--		will be the seven segment led on the same board. 
--		
--Created/Borrowed:	06/23/02 CK 
--
--***********************************************************

--Library declarations
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity accum is  
  port(USER_SET, RST_H : in  std_logic;
	D : in std_logic_vector(3 downto 0);
  	Q : out std_logic_vector(7 downto 0)
	);	-- Input for system clock
	
end accum;

architecture archi of accum is
 	signal tmp: std_logic_vector(7 downto 0);

begin
   process (USER_SET, RST_H) 
      begin        
        if (RST_H='1') then
          tmp <= "00000000"; 
        elsif rising_edge(USER_SET) then
          tmp <= tmp + D;        
        end if;  
  end process;    

  Q <= tmp;

end archi;