--***********************************************************
--File:		Overall control for Lab 6  top.vhd
--
--Purpose:	To introduce students to a top level
--				controlling file.  With large scale
--				projects, one single file must be in 
--				charge and is the one that references
--				all the others.  It references all the 
--				others by creating components of them 
--				within itself.  In this case we will
--				create instances of accum and segment7_
--				controller.  
--		
--Created:	07/01/02 CK and JM 
--
--***********************************************************

--Library declarations
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

--These are the inputs and outputs to the final
--project.  They are by no means all the signals,
--only the final connections to the FPGA.
entity TOP is
    port ( 
	 RST_H : in std_logic;
	 CLK   : in std_logic;
	 USER_SET : in std_logic;
	 DATA     : in std_logic_vector( 7 downto 0 );
	 --
	 SBASE_OUT_H	: out std_logic_vector( 3 downto 0 );	 
	 SSEG_OUT_H 	: out std_logic_vector( 6 downto 0 )
	 );
end TOP;

--Describing "behaviorally" how the system will function.
architecture behavioral of TOP is
	
--This is how I reference the signals within the 
--accumvhd.vhd file.  By doing this, top can see
--down into that file and have access to it's signals.
	component ACCUM
	   port(USER_SET, RST_H : in  std_logic;
			D : in std_logic_vector(3 downto 0);
  			Q : out std_logic_vector(7 downto 0)
			);	-- Input for system clock
	end component ACCUM;

--Just as was done for accum, this gives access to the
--seven segment controller from within top.
	component SEGMENT7_CONTROLLER 
		port ( 
			CLK 	: in std_logic;	-- Input for system clock
			RST_H : in std_logic;	-- Global reset
			--
			SSEG_0_H : in std_logic_vector( 3 downto 0 );	-- Segment 0 input
			DP_0_H 	: in std_logic;								-- Segment 0 decimal point input
			--
			SSEG_1_H : in std_logic_vector( 3 downto 0 );	-- Segment 1 input
			DP_1_H 	: in std_logic;								-- Segment 1 decimal point input
			--
			SSEG_2_H : in std_logic_vector( 3 downto 0 );	-- Segment 2 input
			DP_2_H 	: in std_logic;								-- Segment 2 decimal point input
			--
			SSEG_3_H : in std_logic_vector( 3 downto 0 );	-- Segment 3 input
			DP_3_H 	: in std_logic;								-- Segment 3 decimal point input
			--
			SBASE_OUT_H	: out std_logic_vector( 3 downto 0 );	-- Segment enable output 
			--
			SSEG_OUT_H 	: out std_logic_vector( 6 downto 0 )	-- LED enable output
			);
	 end component SEGMENT7_CONTROLLER; 

--Additional signals to disable segments 2 and 3 that you 
--will have to modify to bring your inputs in.
	 signal INNER_Q : std_logic_vector( 7 downto 0 ); --used to split 8 bits into 2sets of 4
	 signal LOW     : std_logic;  --used to drive decimal point low. not needed this project
	 signal LOW_BUS : std_logic_vector( 3 downto 0 );	--used for segments 2 and 3

--Start of the real work within the file
begin

	LOW <= '0'; --used to disable decimal point
	LOW_BUS <= ( others => '0' ); --tie all bits of LOW_BUS to zero 
											--to be used with segment 2 and 3

	ACCUM1 : ACCUM port map (
		USER_SET => USER_SET, --accumulate button
		RST_H => RST_H, --reset button
		D => DATA( 3 downto 0 ), --four switch input
  		Q => INNER_Q --seven segment output temp for working
		);	

	SEVENSEG : SEGMENT7_CONTROLLER port map ( 
			CLK => CLK, --internal clock for refresh
			RST_H => RST_H, --reset
			--
			SSEG_0_H => INNER_Q( 7 downto 4 ),
			DP_0_H 	=> LOW, --disabled
			--
			SSEG_1_H => INNER_Q( 3 downto 0 ),
			DP_1_H 	=> LOW, --disabled
			--
			SSEG_2_H => LOW_BUS,--disabled 
			DP_2_H 	=> LOW, --disabled
			--
			SSEG_3_H => LOW_BUS, --disabled
			DP_3_H 	=> LOW, --disabled
			--
			SBASE_OUT_H	=> SBASE_OUT_H, --determine input segments
			--
			SSEG_OUT_H 	=> SSEG_OUT_H --LED enable outputs
			);


end behavioral; --end of program