--***********************************************************
--File:		Test bench for Accumulator for Lab 6
--				accumvhd_tb.vhd
--
--Purpose:	To introduce students to accumulators
--		and their functions.  This project source code
--    was originally taken from toolbox.xilinx.com
--    but was modifed for our purposes.  It has a 
--    four bit input and an eight bit output/accumulator
--		capability.  The inputs will be the four switches
--		from the digilent XLA3 board and the output
--		will be the seven segment led on the same board. 
--		
--Created/Borrowed:	06/23/02 CK 
--
--***********************************************************

--Library declarations
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT accum
	PORT(
		USER_SET : IN std_logic;
		RST_H : IN std_logic;
		D : IN std_logic_vector(3 downto 0);          
		Q : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	SIGNAL USER_SET :  std_logic;
	SIGNAL RST_H :  std_logic;
	SIGNAL D :  std_logic_vector(3 downto 0);
	SIGNAL Q :  std_logic_vector(7 downto 0);

	constant CLK_PERIOD : time:= 20 ns;

BEGIN

	uut: accum PORT MAP(
		USER_SET => USER_SET,
		RST_H => RST_H,
		D => D,
		Q => Q
	);

--Clock for USER_SET
CLOCK: process
   begin
     USER_SET <= '0';
     wait for CLK_PERIOD;
     USER_SET <= '1';
     wait for CLK_PERIOD;
end process;

--Clock for RST_H
CLOCK2: process
   begin
     RST_H <= '1';
     wait for CLK_PERIOD*3;
     RST_H <= '0';
     wait for CLK_PERIOD*500;
end process;

--Clock for D
CLOCK3: process
   begin
     D <= "0000";
     wait for CLK_PERIOD*2;
     D <= "0001";
     wait for CLK_PERIOD*2;
end process;


END;