Lab 6 Lecture - Introduction to Accumulators, Floorplanner
and Spartan XL FPGAs
Objectives:
- Understand basic principles concerning FPGAs and the difference
between FPGA and CPLD devices.
- Using the Digilent SpartanXL prototyping board, develop larger
projects by using multiple file projects.
- Introduction to accumulators
- Introduction to Floor Planner
- Introduction to Seven Segment Controller
Theory:
Xilinx FPGA Introduction
The workhorse of the programmable logic industry is the FPGA (Field
Programmable Gate Array). A useful term here is useable or system
gates. If you remember the work you did earlier in the semester
with the 7400 chip you will recall that the chip contained four
two input NAND gates. Given the belief that any logic can be developed
using enough two input NAND gates, this measure has been assigned
the useable/system gates term. The digilent boards (containing the
Xilinx SpartanXL FPGA chips) we will be using for the rest of the
semester are described as having 10 thousand useable gates. This
is the same thing as saying 10 thousand two input NAND gates. It
can do up to that amount of processing. This FPGA chip is relatively
inexpensive. We are also in the process of working on several Virtex
FPGAs for research work. These devices emulate 8 million useable
gates and cost around $10,000 each. The chip is about the size of
a quarter. Each day, the number of useable gates increases, as does
the speed. What is the standard today will be considered antique
in the next year or so. The one underlying theme that will continue
to survive is the coding scheme. You can use VHDL to program ANY
CPLD and ANY FPGA. That is why hardware description languages are
critical to know. Here are some slides from a previous Xilinx briefing
that will help to clarify what an FPGA is and the difference between
FPGAs and CPLDs.
As shown above, FPGAs replace discrete logic. Discrete logic is
the devices you used in the first lab where you connected the small
chips with wires. It also points out the fact that it is volatile.
It requires reprogramming after each power cycle (power off and
on).
As shown here, the look up table is the basic building block of
the FPGA. It allows for different functions to be performed based
on your inputs.
Here is a view of the standard FPGA from above the device. This
is the view of what is going on inside of the hardware. You will
see this view from floor planner later in the lab. The basic thing
to remember from here is the fact that you have three basic parts.
The input and output blocks ring the outside of the device. This
makes sense because you have to have some way to connect your device
to the outside world. Inside you have logic blocks (commonly referred
to as CLBs or configurable logic blocks). Connecting all of them
together is the series of programmable interconnects.
Here are two slides about what is going on inside the CLB. The
CLBs are where the previously shown look up tables are put to work.
Within each CLB there are two slices that are identical. This is
where the actual logic of the device is performed. The number of
CLBs per FPGA range from the tens to the thousands. The number of
CLBs limits the size and complexity of the projects that can be
performed on a device. The SpartanXL device on our prototyping boards
have 400 CLBs.
Applications of Programmable Logic
This is one of the hardest areas for even experienced engineers
to grasp and understand. You have now been introduced to FPGAs and
CPLDs. Even though they are both programmable logic, they are not
used in the industry interchangeably. There are different niches
that each of them serve.
Although only a very small list, if you have a project that revolves
around this type of requirement, your choice of device would usually
be a CPLD.
Here is a list that shows the usual requirements where you would
use an FPGA. They are usually best for requirements where you need
an extremely large number of inputs and outputs.
Using the Digilent XL Prototyping board
The board we are going to be using for the rest of the semester
is the Digilent Spartan XL board. It is an excellent prototyping
board. If you are interested in doing additional projects after
this course, there are a large variety of very reasonably priced
boards that are virtually limitless in the span and quantity of
projects you can do. The Xilinx FPGA on the board is a 3.3volt,
10,000 useable gate device. Once again you can see where we are
using lower voltages (3.3 vs. the 5 from the discrete logic) to
conserve power and heat. The trend is towards lower and lower voltages
in programmable logic. The device has a speed grade of 5. This is
the 5C that you see at the bottom of the chip. A large number of
these chips are cut at a single time from a large wafer. The chips
closer to the center of the wafer are of better quality and their
speed is higher (thus a higher number and price). The lower the
number the further from the center of the wafer and thus the slower
the device (and cheaper the cost). For our chip (XC2S30), they come
in speed grades 4 and 5.
We will also begin using more and more files within each project.
This is necessary anytime you wish to increase your level of complexity
and increase the quantity of things you wish to accomplish.
Introduction to Accumulators
Although not covered in your text, accumulators are a major portion
of any large digital logic or DSP project. There is a great deal
of really good information available at http://www.xilinx.com and
some of these notes come from there. Accumulators are very similar
to counters. Accumulators differ from counters in the nature of
the operands of the add and subtract operation. An accumulator can
be up, down, or updown. You can think of an up accumulator (the
type we are using in this project) as a file cabinet. It starts
out empty. If you add two, it now holds the value of two. If you
add three more it now holds five. We will be using four switches
for our inputs so our accumulator will be four bits. This means
we can add between zero and 15 (binary) at one time. We want a rather
large file cabinet/accumulator so we will use two of our seven segment
displays to display our results. This means our output can go up
to "FF" in hex. This means we can accumulate from zero
to 255.
Floorplanner
Just as Chipviewer gave you a chance to look within the CPLD, Floorplanner
gives you a chance to look within the FPGA. Many times, design engineers
will never need this capability. In this course you will never need
it. What we have taken for granted is that your designs are small
and you do not care about the speed at which your circuit operates.
You just click on the buttons, step back and let the software take
over for you. It is a comfortable place. Unfortunately, in the real
world you always want your design to fit on a smaller device and
you always want to make it go just a little faster than the competitor.
This is where Floorplanner becomes your friend. Floorplanner provides
you with a graphical ability to modify how your design is placed
and routed on the chip. It is a graphical placement tool that gives
you control over placing a design into a target FPGA using a drag
and drop paradigm with the mouse pointer.
This lower picture shows you the CLB in row 7, column
8 and how it was wired on a previous project. These two pictures
give you an idea of where we are headed.
Introduction to Seven-Segment Controller
In some of your previous programmable logic labs, you have used
LEDs, which tend to be able to be turned on or off. With the seven
segment display on this board we are actually going to use a controller
for it that will allow it to refresh/flash off and on so quickly
that to our eyes it will appear as if it is on constantly.
|
