Lab 8 Assignment

Your assignment is to implement the MAC system you did with SysGen into the FPGA board. You will need to map the input of the system into switches and buttons, and the output into the 7 segment displays as you already did in past labs. Since you cannot connect the output of the system directly to a 7 segment display you will need an additional subsystem which is provide below (7_segement.vhd). Also, you will need to find a way to avoid the bouncing effect of the buttons (remember lab 6?). Write the top level file for your MAC and all subsystems required and program the design onto the FPGA board.

You will need to incorporate the following files as VHDL modules into your design:

• 7_segment.vhd
• counter_clk.vhd

The counter_clk is used to control the FPGA system clock. See Lab 5 and 6 for information on writing top level files.

Deliverables:

1. The vhdl code for your top level file.
2. The *.ucf file
3. Once you have the design working on the FPGA, demonstrate it to your TA.

Extra credit

1. Make your system display a 2 hexadecimal output

2. Make your system display a 4 hexadecimal output

3. Find out another way (different than the one you use in the first part of the assignment) to avoid the bouncing effect of the buttons.