Lab 8 Lecture - Design Project and Introduction to MATLAB and SysGen

In the laboratory session, you will build a multiplying accumulator using MATLAB and Simulink. You will then use System Generator (Sysgen) to generate vhdl code that you will integrate with a 7-segment controller. You will then program the design onto the FPGA.

MATLAB and Simulink

MATLAB is a programming language, interpreter and modeling environment. It contains extensive mathematical, signal processing, DSP (digital signal processing) and communications libraries. It allows you to plot functions to visualize your data and design.
Simulink is a graphical block editor that provides a visual data flow environment for modeling and simulation of systems. It is an event-driven simulator that contains an extensive library of functions.

System Generator

System generator allows modeling and implementation of DSP systems. It will generate vhdl netlists for Virtex and Spartan devices. By using Sysgen, you can quickly move a DSP algorithm into an FPGA. You can combine Xilinx and Simulink blocks to create a realistic design and analyze data through simulation.