Lab 8 Tutorial - Design Project and Introduction to MATLAB and SysGen

We are going to create a system using Sysgen.

Go to Start, Program Files, MATLAB 6.5 and click MATLAB 6.5. Type simulink in the MATLAB Command Window. This will open the Simulink Library Browser.

Go to File, New and click Model. This will open a new Simulink project. Expand the Simulink section and click Sources . Drag and drop two Random Number blocks into the module.

Expand Xilinx Blockset and click Basic Elements. Drag and drop 2 Gateway In blocks into the module. Rename the one of the Gateway In blocks to DataA . Double click it and make sure the settings match the ones below.

Rename the other Gateway In to DataB and use the same settings as above. The Gateway In and Out blocks connect the Xilinx blocks to outside inputs. Drag and drop 2 Register blocks into the module. Double click one of the Registers. Make sure the settings match the ones below.

Do the same for the other Register. Connect the blocks together as shown below. To connect the blocks draw a line with your mouse from one block to the other.

Add another Gateway In block to the module. Rename it to reg_enable. Double click on it and make sure the settings match the ones below.

Now expand Simulink and click Sources. Add a Constant block to the module. If there is any number other than 1 inside the Constant box you will need to double click the block and change Constant Value to 1. Connect the blocks as shown below.

Expand Xilinx Blockset and click Math. Add a Mult block to the module. Make sure the settings match the ones below.

Add an Accumulator to the module. Make sure the settings match the ones below.

Add another 2 more Gateway In blocks to the module. Rename one of them reset and the other one enable. Set the Output Data Type of both blocks to Boolean like above. Add 2 more Constant blocks. This time, one Constant block needs to be set to 0 and the other to 1. Connect the blocks as shown below.

Expand Xilinx Blockset and click on Basic Elements. Add another Register, Gateway Out and a System Generator block to the module. Rename the Gateway Out to dataOut. Expand Simulink and click Sinks. Add a Scope block to the project. Connect the blocks as shown below.

The System Generator block must be in your project or you will not be able to simulate it, or generate the VHDL netlist. Now that we have finished building the design, we will simulate it. Go to Simulation, and click on Simulation Parameters. Make sure the settings match the ones below.

Double click on the Scope block. Click the Scope Parameters button next to the Print button, shown below.

Make sure the settings match the ones below.

Click the Start Simulation button, shown below.

Click the Autoscale button. It is the icon that looks like binoculars in the Scope window. Your simulation should look similar to this.

Now we need to generate the code using System Generator. Double click on the System Generator icon in the module. Make sure the settings match the ones below. Of course, you will need to browse to the directory where you want to save your project.

Click Generate. You will be notified when generation is complete. Click OK, OK. Now you can save your module and close it. Open Project Navigator and open your project to begin the lab assignment.