Objectives:

By the time the student has completed this lab and it's associated tutorial, the student should be familiar with the following:

1. Using multiplexers in circuit design.
2. Using the Xilinx ISE software and ModelSim to create and verify the
   operation of a simple digital arithmetic design.

Print the worksheet here and turn it in filled out including specified files

Part 1: Multiplexers

Here, you will be using multiplexers to implement a basic subtractor circuit. The multiplexer you will be using is the 8-to-1 multiplexer. You will need to decide how to best set up the control lines and inputs to derive the correct results. It is suggested you use the following design process:

A. Design the circuit on paper.

1. Fill out K-maps for subtractor. Remember that it has three inputs:
   X, Y, and B_IN, and two outputs: D, and B_out. This means you
   will need two K-maps.
2. Design this circuit using the 8-to-1 multiplexers. Look at your
   K-maps and decide how to best setup the control lines, and the
   eight input lines to generate the two correct outputs.
3. Draw the logic diagram for the subtractor. This will give you some
   idea of how much board space you will save when you implement
   the design using multiplexers, rather than basic logic gates.

B. Implement your design on the prototyping boards in the lab. Debug your design and then demonstrate it to your TA.

Part 2: Using Xilinx.

Here, you will take the circuit you designed in Part 1, and implement it using the Xilinx ISE design suite. Recall that the tutorial has shown you how to do this. Multiplexers are represented in VHDL by case-statements. In the 4-to-1 multiplexer example in the tutorial, that meant that we had a case statement with four possible valid results, looking like this:

case XY_IN is
when "00" => DIV_OUT <= BROW_IN;

Successfully completing the first half of the tutorial will be sufficient introduction for this part.