Outline of Topics:

1. Basics -- Introduction to Multiplexers.
2. Digital Arithmetic -- Subtraction.
3. Digital Arithmetic -- Addition.
4. Applications of Multiplexers -- Using MUXes for Addition.
5. Digital Design -- Using IP Cores and Coregen to Simplify Design.

Part 1: Basics -- Introduction to Multiplexers .

The multiplexer is one of the basic building blocks of any digital design system. What it does is it takes a number of inputs and multiplexes them onto a single output line. That is, it can be told to select one of the input lines, and pass it's state to the output line.

Figure 1: A Multiplexer

The input on the A, B, and C lines tells the multiplexer which one of the inputs 0-8 to pass to the output. For example if A = 0, B = 1, and C = 0, then the input line selected to be passed on to the output would be line 2. (This, incidentally, is shown in the image above.)

This property of multiplexers is very useful. As you will see later on, we can use a multiplexer to implement complex logic functions. In terms of practical lab experience, it allows one chip, the multiplexer, to do the job of several simple logic gates. Later on, you will see how to use the multiplexer to implement binary addition and subtraction. However, before you can do this, you need to know something about binary arithmetic.

Part 2: Digital Arithmetic -- Subtraction

A good example of basic digital arithmetic is binary subtraction. Like the other circuits you have seen up to this point, subtraction can be performed using basic combinational logic. What will follow is an example of the simple one bit subtractor.

Figure 2: Basic Subtractor.

From this diagram, you can see that the subtractor has three inputs and two outputs. This will mean that one must generate two different K-maps, one for each output. Here are the functions each line performs.

X,Y - The two numbers to be subtracted.
b - Borrow-in.
B - Borrow-out.
D - Difference. This is the result.

This subtractor will work on two one-bit numbers X and Y. If you want to subtract larger numbers, you can cascade several of these subtractors together. Below is an example of how this is done:

Figure 3: Cascaded Two-Bit Subtractors.

The above example shows us how we can combine subtractors that operate on one bit numbers and combine them to produce a subtractor that can operate on four-bit numbers. For those of you planning on taking advanced courses in the field, this is a ripple-borrow subtractor.

We will now take a moment to examine the basic operation of this device. Below is the truth table for the basic subtractor. You will need to know this in order to complete the first half of the lab.

Figure 4: Truth Table for the Subtractor.

IE 1-0=0 with no borrow out

As a quick thought exercise, recall the multiplexers introduced earlier in the lecture. Think of how one could use them to implement that truth table. Later, you will see how to do it with digital addition.

Part 3: Digital Arithmetic -- Addition.

Recall that in the previous section, we covered the basics of digital subtraction. In this section, we will cover the basics of digital addition. Here is a block that, instead of computing the difference between two numbers, will compute the sum of two numbers. Now, the student should be cautioned that they are not as different as they seem. Later in the course, you will learn about a digital circuit that will be able to do both.

Below is an example of a simple adder.

Figure 5: Basic Adder.

As you can see, it looks very much like the block diagram for the basic subtractor. We have two bits to be added, A and B. The line K is the carry-in, and we have two outputs: The line S is the Sum, and C is the carry-out. Like the subtractor, these can be cascaded together to form an adder that can operate on numbers of any size one would like. If they are configured in a way identical to the cascaded subtractors you saw earlier, the resulting circuit would be called a ripple-carry adder. Below, you will find the truth tables necessary to implement the basic adder.

Figure 6: Truth Table for the Basic Adder

IE 1+1=0 Carry 1

Part IV: Application of Multiplexers -- Using MUXes for Addition.

In this section, you will see how to utilize multiplexers to create an addition circuit. You will not be building an adder, however you can apply this knowledge to the subtractor part of the lab, which requires that you construct a subtractor using multiplexers.

If one utilized the 8-to-1 MUX introduced in Part 1, the student might see that implementation of both outputs would be a straightforward affair. However, what you are more likely to have available is the 4-to-1 MUX shown below:

Figure 7: Block Diagram of a 4-to-1 MUX.

We will use this particular multiplexer for the example.

Now, we will step through the basic design process. We already know we want to build a basic adder. You have the truth-table from Figure 6. Now, we will generate two K-maps. One for the Sum, and one for the Carry Out.

Figure 8: K-map for the Sum

Let's take a few moments to inspect this Karnaugh-map. Note that the Sum is A when B and K are both true or false. Sum is the complement of A when B or K are true, but not both.

Now, how can we use this knowledge to create the Sum from a 4-to-1 MUX?

Recall that the output is either A or the complement of A. This makes things easier.

Also, notice how the 4-to-1 MUX has two control lines, S1, and S2. Recall that the value on the control lines determins which input line is passed to the output.

Here is the solution:

If we tie B to S1 and K to S2, then we can tie A to input lines 1 and 4. (00 and 11.) Then we must tie the complement of A to input lines 2 and 3 (01 and 10). This allows us to use a 4-to-1 MUX to produce the Sum.

Now, we have to address the Carry Out output.

Figure 9: K-map for the Carry-Out.

Now, inspect this K-map for a moment. Think of how we could use this K-map to produce the Carry-Out using a 4-to-1 MUX.

Note that when B and K are both false, then the output is also false.
Note that when B and K are both true, then the output is also true.
Finally, note that when B or K are true, but not both, the output is A.

So, if we again apply B to S1 and K to S2, we can generate the correct Carry-Out by tying input line 1 to ground, input line 4 to Vcc, and both input lines 2 and 3 to A. This will generate the correct output. And, here, you can see that we can build a simple one-bit adder using just two 4-to-1 MUXes.

However, in the next section, we will briefly discuss the world of digital design, the way it is carried out in the industry today. The ICs you are using now make for a useful introduction to the basics of digital logic. However, actual digital design is carried out in a much different way. To read more about this, continue on to Part 5.

Part 5: Digital Design -- Using IP Cores to Simplify Design.

In the world of digital design, one uses Hardware Description Languages to describe complex logic functions. These are encapsulated into design suites such as Xilinx's ISE and similar tools. However, if a digital engineer were to code an adder, or create a cosine lookup table each time he or she were on a project, the engineer would be wasting his or her time by reinventing the wheel. Alternatively, if the design engineer had to continually re-code commonly used complex digital circuits in large projects; they would end up wasting even more time and money.

Because of this, a digital design engineer may just use an IP core. An IP core (IP here stands for Intellectual Property) is a block of HDL code that other engineers have already written to perform a specific function. You can think of it as a class in C++. It is a specific piece of code designed to do a specific job. One can use these cores in a complex design where an engineer wants to save the time he or she might have otherwise used to design the given function from scratch.

As with any engineering tool, IP cores have their advantages and disadvantages. Though an IP core may simplify a given design, the engineer has to design the whole project around the requirements of the IP core. And while an IP core may reduce design time, the engineer frequently has to pay for the right to use the core, (as it is somebody else's intellectual property.)

The Xilinx software loaded on the computers in the EECE building has a complete library of IP cores. In the lab, you will be given the chance to incorporate an IP core into a simple project.