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Lab 4 - Introduction to Sequence Detectors and Coolrunner CPLDs Objectives: Implement a sequence recognizer that will identify or detect a specific sequence of highs and lows using ISE software and then transfer the project to a Coolrunner CPLD. The tutorial will take you from start to finish through an entire project. You will then be required to repeat the process with a different sequence. Sequence Recognizer and Xilinx Coolrunner CPLD. The tutorial will take you from start to finish for a sequence detector that will recognize the sequence 10010. It is strongly recommended that you go slowly and completely through the entire tutorial before you begin your assignment. Your assignment is to write the VHDL code for a sequence recognizer that will recognize the sequence 1010. You will need to write the VHDL, the test bench (make your simulation look similar to mine in the tutorial), program the CPLD and then demonstrate it for your TA. It is not critical that you use the same time constraints as the tutorial in your simulation. What is critical is that you note that as long as your reset is high, you stay in state A (your initial state). Once your reset drops and you get a rising edge on your clock, you run your sequence through and verify that your code transitions through each of the states and finally causes your output to go high. Another thing to pay particular attention to is the fact that you only have one state high at a time (Z is not a state). This is called one hot. The deliverables for this portion of the project are listed below. It would behoove you to read the deliverables and the worksheet before you start the tutorial so that you know what you are going to be looking for. Deliverables for lab 4
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alnz - Last update: June 21, 2004