library IEEE;
use IEEE.std_logic_1164.all;

entity subtraction is
port (
	BROW_IN	: in STD_LOGIC; -- borrow in
	XY_IN		: in STD_LOGIC_VECTOR (1 downto 0);

-- Note that we are using the data type "std_logic_vector"
-- for the first time. This data type can be 1 to n bits
-- wide (n-1 downto 0). In our case, XY_IN is two bit wide.
-- XY_IN(1) (bit 1 of signal XY_IN) will be one of the inputs
-- for the substractor. XY_IN(0) (bit 0 of signal XY_IN) 
-- will be the second input.

	BROW_OUT	: out STD_LOGIC; -- borrow out
	DIFF_OUT	: out STD_LOGIC  -- difference
);
end subtraction;

architecture subtraction_arch of subtraction is
begin

-- 4 to 1 multiplexer design with case construct
-- SEL: in STD_LOGIC_VECTOR(1 downto 0);
-- A, B, C, D:in STD_LOGIC;
-- MUX_OUT: out STD_LOGIC;

OUT_DIFF:
process (XY_IN, BROW_IN)
begin

case XY_IN is
	when "00" => DIV_OUT <= BROW_IN;
	when "01" => DIV_OUT <= not(BROW_IN);
	when "10" => DIV_OUT <= not(BROW_IN);
	when "11" => DIV_OUT <= BROW_IN;
	when others => DIV_OUT <= 'Z';
end case;

-- In "case" construct, you must include a case for
-- each possible set of inputs. The "when others" line
-- takes care of any other inputs that may exist. Note
-- that "1" and "0" are not the only possible logic states.
-- For instance, what is the meaning of the logic state "Z" ??

end process;

-- 4 to 1 multiplexer design with case construct
-- SEL: in STD_LOGIC_VECTOR(1 downto 0);
-- A, B, C, D:in STD_LOGIC;
-- MUX_OUT: out STD_LOGIC;

OUT_BROW:
process (XY_IN, BROW_IN)
begin

case XY_IN is
	when "00" => BROW_OUT <= ???; -- complete this line!
	when "01" => BROW_OUT <= ???; -- complete this line!
	when "10" => BROW_OUT <= ???; -- complete this line!
	when "11" => BROW_OUT <= ???; -- complete this line!
	when others => DIV_OUT <= 'Z';
end case;

end process; 

end subtraction_arch;