library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

-- synopsys translate_off
library UNISIM;
library XilinxCoreLib;
-- synopsys translate_on

entity complement is
port (
a: IN std_logic_VECTOR(4 downto 0); 
clk: IN std_logic;
bypass: IN std_logic;
q: OUT std_logic_VECTOR(5 downto 0)
);
end complement;

architecture RTL of complement is
-------------------------------------------------------------------------
--
-- Component Declaration
--
-- The following lines were taken directly from the twos_comp.vho file
-- that Coregen creates for you. It is created in such a way that the
-- designer has to simply cut and paste the Component Declaration statements
-- into the source code as I have done here. The twos_comp.vho file I 
-- added to the project so you will see it in the Sources Window. Typically
-- it is just created in the project directory and you can get to it from
-- any text editor
--------------------------------------------------------------------------

--**PASTE THE COMPONENT DECLARATION HERE**


begin
-------------------------------------------------------------------------
--
-- Component Instantiation
--
-- The following lines were taken directly from the twos_comp.vho file
-- that Coregen creates for you. It is created in such a way that the
-- designer has to simply cut and paste the Component Instantiation statements
-- into the source code as I have done here. The twos_comp.vho file I 
-- added to the project so you will see it in the Sources Window. Typically
-- it is just created in the project directory and you can get to it from
-- any text editor
--------------------------------------------------------------------------

--**PASTE THE TWOS_COMP PORT MAP HERE**

end RTL;