--***********************************************************
-- File:		Sequence Detector 
--		
-- Created:	01/18/01 TB
-- Modified:	5/27/01 CK modified sequence and added 
--		additional outputs.
-- Modified:	4/23/02 CK modified to add comments and 
--		additional libraries.  
--	Modified: 	6/04/04 AV modified to add comments and
--		solve compatibilites with new lab manual and ISE 6.2
--***********************************************************

--Library declarations

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity sequence is
  port(
  		clk	:in std_logic;
		reset	:in std_logic;
		X		:in std_logic;
  		Z		:out std_logic_vector (4 downto 0)
													-- 4 downto 0 means it has
													-- bit 4, bit 3, bit 2, bit 1
													-- bit 0; a signal 5 bits wide
		);
end sequence;

architecture behavoiral of sequence is

--**************************************************
-- User data types and signals are declared here
  type state_type is (A, B, C, D, E, F);
  signal state, next_state : state_type;
--**************************************************
begin

--**************************************************
-- Processes of the architecture are declared here.
-- state_register defines behavoir when a reset signal
-- is given.

state_register: process (clk, reset) 		-- Sensible signals 
  begin
    if (reset = '1') then						--if reset is high, goto state A
       state <= A;
    elsif (clk'event and clk = '1') then 	--if not, and rising 
       state <= next_state;					--edge, go to next state
    end if;
end process;  

--**************************************************
-- next_state process steps through each state 
-- based on state diagram

next_state_func: process (X, state)
begin 
  case state is 
      when A =>						  			-- if we are in state A
          if X = '1' then			  			-- and '1' is received in the input X
             next_state <= B;		  			-- the system goes to state B
          else 						 	
             next_state <= A;		  			-- else, system stays in state A
          end if;
      when B =>
           if X = '1' then
             next_state <= B;
           else
             next_state <= C;
           end if;
      when C =>
           if X = '1' then
              next_state <= B;
           else 
              next_state <= D;
           end if;
      when D =>
           if X ='1' then
              next_state <= E;
           else
              next_state <= A;
           end if;
      when E =>
           if X = '1' then
              next_state <= B;
           else
              next_state <= F;
           end if;
      when F =>
           if X = '1' then
              next_state <= B;
           else
              next_state <= A;                       
           end if;
      end case;
end process;

--**************************************************
-- Third process: definition of outputs according to
-- the state of the system

output_func:  process (X, state)
  begin
  	case state is 
      when A => Z <= "00000";
      when B => Z <= "00001";
      when C => Z <= "00010";
      when D => Z <= "00100";
      when E => Z <= "01000";
      when F => Z <= "10000";
    end case;
  end process;

end;