--*********************************************
-- File: fewgates.vhd
--Name:
--Date:
--Lab Partner:
--*********************************************
--Defining the library packages to be used

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Declaration of the module's inputs and outputs
entity fewgates is 
port (
	a: in std_logic;
	b: in std_logic;
end fewgates;

--Defining the module's behavior
Architecture behavioral of fewgates is 
begin
	process (a,b,s) 
	begin 

  	end process;
end behavioral;