LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

--Declaration of ModelSim libraries used
LIBRARY UNISIM;
LIBRARY XILINXCORELIB;

ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS
-- This is the one of the components we will be simulating.
component twos_comp is
port (
	A: IN std_logic_VECTOR(4 downto 0);
	CLK: IN std_logic;
	bypass: IN std_logic
	Q: OUT std_logic_VECTOR(5 downto 0)
	);
end component;

SIGNAL a_data_in : std_logic_VECTOR(4 downto 0);
SIGNAL clock_in : std_logic;
signal bypass_in : std_logic;
SIGNAL q_data_out : std_logic_VECTOR(5 downto 0);

--Defining the variable "CLK_PERIOD" to be
--equal to 20 nano seconds
constant CLK_PERIOD : time:= 20 ns;

BEGIN
	--Unit under test is the module complement. Notice 
	--that it is not case sensitive
	UUT : twos_comp
	--Defining external interface signals. This 
	--associates ports of the named entity with
	--signals in the current architecture.
	PORT MAP (
		A => a_data_in,
		CLK => clock_in,
		bypass => bypass_in,
		Q => q_data_out
	);

	-- Applying a clock to the system.
	main_clock : PROCESS
	BEGIN
		clock_in <= '0';
		wait for CLK_PERIOD;
		clock_in <= '1';
		wait for CLK_PERIOD;
	END PROCESS; 

	-- Feeding in different data sets at different times:
	data_procs : PROCESS
	BEGIN
		a_data_in <= "00001";
		wait for CLK_PERIOD * 8;
		a_data_in <= "11111";
		wait for CLK_PERIOD * 8;
		a_data_in <= "01111";
		wait for CLK_PERIOD * 8;
		a_data_in <= "10000";
		wait for CLK_PERIOD * 8;
	END PROCESS;

	bypass_signal : PROCESS
	BEGIN
		bypass_in <= '0';
		wait for 500*CLK_PERIOD;
	END PROCESS;

END testbench_arch;