library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity black_box is
Port( 
	a 	: in std_logic_vector(4 downto 0);
	b 	: in std_logic_vector(4 downto 0);
	add_sub : in std_logic;
	CLK 	: in std_logic;
	output : out std_logic_vector(4 downto 0)
	);
end black_box;

architecture Structural of black_box is

-- COMPONENT DECLARATION SECTION --
-- SIGNALS DECLARATION SECTION --

begin

-- COMPONENT INSTANTIATION SECTION --

end Structural;