--***********************************************************
-- File:		Sequence Detector test bench for Lab 4
--
--
-- Created:	06/03/02 CK
--
-- Modified: 6/04/2004 AV to solve incompatibilities with
--		new lab manual and ISE 6.2
--***********************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT sequence
	PORT(
		clk 	: IN std_logic;
		reset : IN std_logic;
		X 		: IN std_logic;          
		Z 		: OUT std_logic_vector(4 downto 0)
		);
	END COMPONENT;

	SIGNAL CLK :  std_logic;
	SIGNAL RESET :  std_logic;
	SIGNAL X :  std_logic;
	SIGNAL Z :  std_logic_vector(4 downto 0);

	constant CLK_PERIOD : time:= 20 ns;
	constant CLK_CYCLE  : time:= 40 ns;

BEGIN

	uut: sequence PORT MAP(
		clk => clk,
		reset => reset,
		X => X,
		Z => Z
			);


-- *** Test Bench - User Defined Section ***
--
-- This is where I begin inserting my processes

-- Clock for CLK
-- All I want is to toggle the clock off and on

clock_signal: process
   begin
     CLK <= '0';
       wait for CLK_PERIOD;
     CLK <= '1';
       wait for CLK_PERIOD;
end process;	 -- NOTE: a CLK_CYCLE = 2 x CLK_PERIOD

--  Reset signal generation:
--  For reset I wanted to tie it high for a 
--  short period of time and then tie it low
--  for a really long time.

reset_signal: process
   begin
     RESET <= '1';
       wait for CLK_PERIOD*4;
     RESET <= '0';
       wait for CLK_PERIOD*500;
end process;

--  Following lines specify the input sequence X
--  X signal generation:
--  X is set up to repeat 100100 over and over again.

x_signal: process
   begin
	  X <= '0';
	    wait for CLK_PERIOD*4.5;	-- We introduce this delay to
		 									-- start the desired input sequence
											-- after the reset is set to 0.

     X <= '1';							-- Here the sequence starts, the reset
	  										-- was set to zero half a CLK_PERIOD ago.
       wait for CLK_CYCLE;
     X <= '0';
       wait for CLK_CYCLE;
     X <= '0';
       wait for CLK_CYCLE;
     X <= '1';
       wait for CLK_CYCLE;
     X <= '0';
       wait for CLK_CYCLE;
     X <= '0';
       wait for CLK_CYCLE*500;	-- this is just a way to say that X will
		 									-- stay in zero til the "infity"
	end process;
-- *** End Test Bench - User Defined Section ***

END;