--***********************************************************
-- File:		Display controller
--		
-- Created:	07/06/2004 AV
--***********************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity disp_controller is
    Port ( msd : in std_logic_vector(3 downto 0);
           lsd : in std_logic_vector(3 downto 0);
           clk : in std_logic;
           anodes : out std_logic_vector(6 downto 0);
           cat1 : out std_logic;
           cat2 : out std_logic);
end disp_controller;

architecture structural of disp_controller is

--*****************************************************
-- Components declarations -- 
--*****************************************************

	COMPONENT selector
	PORT( ?? complete!! ??
		);
	END COMPONENT;

	COMPONENT conventer
	PORT( ?? complete!! ??
		);
	END COMPONENT;

-- use inv_v (inverter) as an example: 

	COMPONENT  inv_v
	PORT(
		o : OUT std_ulogic;
		i : IN std_ulogic
		);
	END COMPONENT;

--*****************************************************
-- Signals declarations -- 
--*****************************************************

	signal converter_in : std_logic_vector (3 downto 0);
begin

--*****************************************************
-- Components Instantiations -- 
--*****************************************************

	Inst_selector: selector PORT MAP(
		msd => ??,
		lsd => ??,
		sel => ??,
		selector_out => ??
	);

	Inst_conventer: conventer PORT MAP(
		digit_in => ??,
		digit_out => ?? 
	);

-- use inv_v instantiation as an example:

	Inst_inversor: inv_v PORT MAP(
		o => cat2,
		i => clk
	);

	cat1 <= clk;

end structural;

-- The format to complete instantiations is as follow:
-- name_of_component_input/output => name_of_wire(signal)_to_connect_to,
-- Where:
-- name_of_component_input/output is the name of one of the component's port
-- and
-- name_of_wire(signal)_to_connect_to is the name of whatever goes connected
-- to the component in that port. Note that it can be the same as 
-- name_of_component_input/output or it can be a signal (a wire in the system)
-- Note that if you use a signal you will need to declare it !!!