-- VHDL Test Bench Created from source file disp_controller.vhd -- 22:59:42 07/11/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;

ENTITY disp_testbench IS
END disp_testbench;

ARCHITECTURE behavior OF disp_testbench IS 

	COMPONENT disp_controller
	PORT(
		msd : IN std_logic_vector(3 downto 0);
		lsd : IN std_logic_vector(3 downto 0);
		clk : IN std_logic;          
		anodes : OUT std_logic_vector(6 downto 0);
		cat1 : OUT std_logic;
		cat2 : OUT std_logic
		);
	END COMPONENT;

	constant CLK_PERIOD : time := 20 ns;

	SIGNAL msd :  std_logic_vector(3 downto 0);
	SIGNAL lsd :  std_logic_vector(3 downto 0);
	SIGNAL clk :  std_logic;
	SIGNAL anodes :  std_logic_vector(6 downto 0);
	SIGNAL cat1 :  std_logic;
	SIGNAL cat2 :  std_logic;

BEGIN

	uut: disp_controller PORT MAP(
		msd => msd,
		lsd => lsd,
		clk => clk,
		anodes => anodes,
		cat1 => cat1,
		cat2 => cat2
	);


-- *** Test Bench - User Defined Section ***
   clock_signal : PROCESS
   BEGIN
	clk <= '0';
   	wait for CLK_PERIOD;
   	clk <= '1';
   	wait for CLK_PERIOD;
   END PROCESS;

   msb_signal : PROCESS
   begin
   	msd <= "0000";
	wait for 2*CLK_PERIOD;
	msd <= "0001";
	wait	for 2*CLK_PERIOD;
	msd <= "0010";
	wait	for 2*CLK_PERIOD;
   	msd <= "0011";
	wait for 2*CLK_PERIOD;
	msd <= "0100";
	wait	for 2*CLK_PERIOD;
	msd <= "0101";
	wait	for 2*CLK_PERIOD;
   	msd <= "0110";
	wait for 2*CLK_PERIOD;
	msd <= "0111";
	wait	for 2*CLK_PERIOD;
	msd <= "1000";
	wait	for 2*CLK_PERIOD;
   	msd <= "1001";
	wait for 2*CLK_PERIOD;
	msd <= "1010";
	wait	for 2*CLK_PERIOD;
	msd <= "1011";
	wait	for 2*CLK_PERIOD;
   	msd <= "1100";
	wait for 2*CLK_PERIOD;
	msd <= "1101";
	wait	for 2*CLK_PERIOD;
	msd <= "1110";
	wait	for 2*CLK_PERIOD;
   	msd <= "1111";
   end process;

lsd_signal : process

   begin
   	lsd <= "1111";
	wait for 2*CLK_PERIOD;
	lsd <= "1110";
	wait	for 2*CLK_PERIOD;
	lsd <= "1101";
	wait	for 2*CLK_PERIOD;
   	lsd <= "1100";
	wait for 2*CLK_PERIOD;
	lsd <= "1011";
	wait	for 2*CLK_PERIOD;
	lsd <= "1010";
	wait	for 2*CLK_PERIOD;
   	lsd <= "1001";
	wait for 2*CLK_PERIOD;
	lsd <= "1000";
	wait	for 2*CLK_PERIOD;
	lsd <= "0111";
	wait	for 2*CLK_PERIOD;
   	lsd <= "0110";
	wait for 2*CLK_PERIOD;
	lsd <= "0101";
	wait	for 2*CLK_PERIOD;
	lsd <= "0100";
	wait	for 2*CLK_PERIOD;
   	lsd <= "0011";
	wait for 2*CLK_PERIOD;
	lsd <= "0010";
	wait	for 2*CLK_PERIOD;
	lsd <= "0001";
	wait	for 2*CLK_PERIOD;
   	lsd <= "0000";
   end process;

-- *** End Test Bench - User Defined Section ***

END;