--***********************************************************
-- File:		inversor
--		
-- Created:	07/06/2004 AV
--***********************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity inv_v is
    Port ( i : in std_logic;
           o : out std_logic);
end inv_v;

architecture Behavioral of inv_v is

begin

o <= not (i);

end Behavioral;