--*********************************************
-- File: fewgates.vhd
--Name:
--Date:
--Lab Partner:
--*********************************************
--Defining the library packages to be used


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Declaration of the module's inputs and outputs
ENTITY fewgates IS
	PORT (
		A: in std_logic;
		B: in std_logic;
		C: in std_logic;
		Y: out std_logic
	); 
END fewgates;

--Defining the modules behavior
ARCHITECTURE c1_behavior of fewgates is 
SIGNAL sig1: std_logic;

BEGIN
	PROCESS (A, B, C) 
      BEGIN 
  		sig1 <= (NOT A) AND (NOT B);
  		Y <=  C OR sig1; 
	  END PROCESS;
END c1_behavior;