--*********************************************
-- File: fewgates.vhd
--Name:
--Date:
--Lab Partner:
--*********************************************
--Defining the library packages to be used


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Declaration of the module's inputs and outputs
ENTITY fewgates2 IS
	PORT (
		X: in  std_logic;
		V: in  std_logic;
		W: in  std_logic;
		Z: in  std_logic;
    	O: out std_logic
	);  
END fewgates2;


--Defining the modules behavior
ARCHITECTURE behavioral OF fewgates2 IS 

COMPONENT fewgates
	PORT(
			A   : in STD_LOGIC; 
			B	: in STD_LOGIC;
			C	: in STD_LOGIC;
			Y	: out STD_LOGIC
	);
END COMPONENT;

SIGNAL sig1: std_logic;
SIGNAL sig2: std_logic;

BEGIN
    -- Here we are connecting fewgate's pins
	fg1: fewgates PORT MAP(
		A 		=> X, 
		B     	=> V,
		C  	    => sig1,
		Y		=> sig2
	);
 
	P1: PROCESS(W, Z) 
    BEGIN 
  		sig1 <= W AND Z;
 	END PROCESS;

    P2: PROCESS(sig2)
    BEGIN
    	O <= NOT(sig2);
    END PROCESS;

END behavioral;