--***********************************************************
-- File:		Converter
--		
-- Created:	07/06/2004 AV
--***********************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity conventer is
    Port ( digit_in : in std_logic_vector(3 downto 0);
           digit_out : out std_logic_vector(6 downto 0));
end conventer;

architecture Behavioral of conventer is

begin

dig_to_sseven_segment: process (digit_in)

begin

case digit_in is

	   when "0000" => digit_out <= "0111111";
	   when "0001" => digit_out <= "0000110";
	   when "0010"	=> digit_out <= "1011011";
	   when "0011" => digit_out <= "1001111";
	   when "0100" => digit_out <= "1100110";
	   when "0101" => digit_out <= "1101101";
	   when "0110" => digit_out <= "1111101";
	   when "0111" => digit_out <= "0000111";
	   when "1000" => digit_out <= "1111111";
	   when "1001" => digit_out <= "1101111";
	   when "1010" => digit_out <= "1110111";
	   when "1011"	=> digit_out <= "1111100";
	   when "1100" => digit_out <= "0111001";
	   when "1101" => digit_out <= "1011110";
	   when "1110" => digit_out <= "1111001";
	   when "1111" => digit_out <= "1110001";
	   when others => digit_out <= "0000000";
end case;

end process;

end Behavioral;