--***********************************************************
-- File:		Selector
--		
-- Created:	07/06/2004 AV
--***********************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity selector is
    Port ( msd : in std_logic_vector(3 downto 0);
           lsd : in std_logic_vector(3 downto 0);
           sel : in std_logic;
           selector_out : out std_logic_vector(3 downto 0));
end selector;

architecture Behavioral of selector is

begin
selection : process (sel, lsd, msd)
begin

if sel = '0' then
	selector_out <= lsd;
else
	selector_out <= msd;
end if;

end process;

end Behavioral;