library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity four_bit_reg is
    Port ( i : in std_logic_vector(3 downto 0);
           reset : in std_logic;
		 clk : in std_logic;
           o : out std_logic_vector(3 downto 0));
end four_bit_reg;

architecture Behavioral of four_bit_reg is

begin
reg : process (clk, reset)
begin
if rising_edge(clk) then
	if reset <= '0' then
		o <= i;
	else 
		o<= "0000";
	end if;
end if;
end process;
end Behavioral;