-- VHDL Test Bench Created from source file half_adder.vhd -- 14:11:11 07/20/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT half_adder
	PORT(
		x : IN std_logic;
		y : IN std_logic;          
		s : OUT std_logic;
		c : OUT std_logic
		);
	END COMPONENT;

	SIGNAL x :  std_logic;
	SIGNAL y :  std_logic;
	SIGNAL s :  std_logic;
	SIGNAL c :  std_logic;

	constant CLK_PERIOD : time:= 20 ns;

BEGIN

	uut: half_adder PORT MAP(
		x => x,
		y => y,
		s => s,
		c => c
	);


-- *** Test Bench - User Defined Section ***
   x_signal : PROCESS
   BEGIN
      x <= '0';
	 wait for 10*clk_period;
	 x <= '1'; 
	 wait for 20*clk_period;
   END PROCESS;

   y_signal : process
   begin
   	y <= '0';
	wait for 20*clk_period;
	y <= '1';
	wait for 20*clk_period;
   end process;

-- *** End Test Bench - User Defined Section ***

END;