LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY addition IS
  PORT (
	A	: IN  STD_LOGIC;
	B	: IN  STD_LOGIC;
	K	: IN  STD_LOGIC; 
	S	: OUT STD_LOGIC;
	C	: OUT STD_LOGIC  
  );
END addition;

ARCHITECTURE addition_arch OF addition IS

SIGNAL sig1:	STD_LOGIC_VECTOR(1 DOWNTO 0);

BEGIN 

	sig1(1) <= B;
	sig1(0) <= K;

	P1: process (sig1, A)
	BEGIN
		CASE sig1 IS   -- MULTIPLEXOR FOR S
			WHEN "00" => 	S <= A;
			WHEN "01" => 	S <= NOT(A);
			WHEN "10" => 	S <= NOT(A);
			WHEN OTHERS=> 	S <= A;
		END CASE;
	END PROCESS;

	P2: process (sig1, A)
	BEGIN
		CASE sig1 IS   -- MULTIPLEXOR FOR S
			WHEN "00" => 	C <= '0';
			WHEN "01" => 	C <=  A;
			WHEN "10" => 	C <=  A;
			WHEN OTHERS=> 	C <= '1';
		END CASE;
	END PROCESS;
END addition_arch;