-- VHDL Test Bench Created from source file black_box.vhd -- 21:29:08 10/04/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY black_box_top_tb_vhd_tb IS
END black_box_top_tb_vhd_tb;

ARCHITECTURE behavior OF black_box_top_tb_vhd_tb IS 

	COMPONENT black_box
	PORT(
		a : IN std_logic_vector(4 downto 0);
		b : IN std_logic_vector(4 downto 0);
		add_sub : IN std_logic;
		CLK : IN std_logic;          
		output : OUT std_logic_vector(4 downto 0)
		);
	END COMPONENT;

	SIGNAL a :  std_logic_vector(4 downto 0);
	SIGNAL b :  std_logic_vector(4 downto 0);
	SIGNAL output :  std_logic_vector(4 downto 0);
	SIGNAL add_sub :  std_logic;
	SIGNAL CLK :  std_logic;
	constant CLK_PERIOD : time:= 20 ns;
BEGIN

	uut: top PORT MAP(
		a => a,
		b => b,
		output => output,
		add_sub => add_sub,
		CLK => CLK
	);


-- Process to describe the clock signal --
-- This process is complete and you can --
-- use it as an example. Dont modify it --
   clk_signal : PROCESS	   
   BEGIN
    CLK <= '0';
    wait for CLK_PERIOD;
    CLK <= '1';
    wait for CLK_PERIOD;
   END PROCESS;

-- Process to describe the values of operand A --

   a_signal : process
   begin
    a <= "?????";
    wait for ??(how long? how many clock cycles??);
    a <= "?????";
    wait for ??(how long? how many clock cycles??);
    a <= "?????";
    wait for ??(how long? how many clock cycles??);
-- after this, the signal will repeat the process --
    end process;

-- Process to describe the values of operand A --

    b_signal : process
    begin
    b <= "?????";
    wait for ??(how long? how many clock cycles??);
    b <= "?????";
    wait for ??(how long? how many clock cycles??);
    b <= "?????";
    wait for ??(how long? how many clock cycles??);
-- after this, the signal will repeat the process --
    end process;

-- Process to describe the values of bypass signal --

    bypass_signal : process
    begin
    add_sub <= "?????";
    wait for ??(how long? how many clock cycles??);
    add_sub <= "?????";
    wait for ??(how long? how many clock cycles??);
    add_sub <= "?????";
    wait for ??(how long? how many clock cycles??);
-- after this, the signal will repeat the process --
    end process;

END;