library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.comes.all;

ENTITY black_box IS
    PORT ( 
		a 		: IN  std_logic_vector(2 DOWNTO 0);
        b 		: IN  std_logic_vector(2 DOWNTO 0);
		add_sub : IN  std_logic;
        output 	: OUT std_logic_vector(2 DOWNTO 0)
		 );
END black_box;

ARCHITECTURE Structural OF black_box IS

	COMPONENT complement
		PORT (
			a			: IN std_logic_VECTOR(2 downto 0); 
			bypass		: IN std_logic;
			q			: OUT std_logic_VECTOR(2 downto 0)
		);
	END COMPONENT;

	COMPONENT adder
		PORT (
			x		    : in STD_LOGIC_VECTOR(2 DOWNTO 0); 
			y			: in STD_LOGIC_VECTOR(2 DOWNTO 0); 
			c_out		: out STD_LOGIC;
			s			: out STD_LOGIC_VECTOR(2 DOWNTO 0)
		);
	END COMPONENT;



SIGNAL sig1	: 	STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL aux 	:	STD_LOGIC;

BEGIN 

	comp: complement PORT MAP(
		a => b,
		bypass => add_sub,
		q => sig1
	);

	add1: adder PORT MAP(
		x => a,
		y => sig1,
		c_out => aux,
		s => output
	);
	
END Structural;