LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY seq_det2 IS
	PORT (
		CLK			: IN STD_LOGIC;
		X		    : IN STD_LOGIC;
 		W			: OUT STD_LOGIC
	);
END seq_det2;

ARCHITECTURE seq_det_arch of seq_det2 is

BEGIN


	set_state_process: PROCESS(CLK)
	VARIABLE STATE		: STD_LOGIC_VECTOR(1 DOWNTO 0):= "00";

	BEGIN
		IF (CLK = '1') THEN
			CASE STATE IS
				WHEN "00" =>
					IF (X = '0') THEN
						STATE := "00";
						W <= '0';
					ELSE
						STATE := "01";
						W <= '0';
					END IF;
				
				WHEN "01" =>
					IF (X = '1') THEN 
						STATE := "10";
						W <= '0';
					ELSE
						STATE := "00";
						W <= '0';
					END IF;

				WHEN "10" =>
					IF (X = '1') THEN 
						STATE := "10";
						W <= '0';
					ELSE
						STATE := "11";
						W <= '1';
					END IF;

				WHEN OTHERS =>
					IF (X = '1') THEN 
						STATE := "01";
						W <= '0';
					ELSE
						STATE := "00";
						W <= '0';
					END IF;
			END CASE;
		END IF;
	END PROCESS;

END seq_det_arch;