--***********************************************************
-- File:		Counter
--		
-- Created:	07/06/2004 AV
--***********************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
    Port ( clk : in std_logic;
           reset : in std_logic;
           pause : in std_logic;
		 count_out : out std_logic_vector(3 downto 0)
		 );
end counter;

architecture Behavioral of counter is

------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------

------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------

signal temporal_count	: std_logic_vector(3 downto 0);--temporary variable for output q[3..0] 
signal fake_clk		: std_logic;				 --Clock divider, adjust to suit your needs.
signal clk_division		: std_logic_vector(2 downto 0) := "000";

begin 

clk_divider : process (clk, clk_division)

begin
	if (clk = '1' and clk'Event) then
		clk_division <= clk_division + 1;
	end if;

fake_clk <= clk_division(2);

end process;

--
-- We will use this fake clock (half the speed of the original one)
-- to avoid having a counter too fast. For implementation we will
-- make the clock even slower
--


counting : process(reset, pause, fake_clk, temporal_count)

begin 
	if reset = '1' and pause = '0' then 
		temporal_count <= "0000"; 					-- Asynchronous reset. 
	elsif reset = '0' and pause = '1' then
		temporal_count <= temporal_count + 0; 			-- Asynchronous count pause. 
	else

		if fake_clk'event and fake_clk='1' then 		-- Counting state for implementation

			if temporal_count < 15 then 
				temporal_count <= temporal_count + 1; 	-- Counter increase 
			else 
				temporal_count <= "0000"; 			-- Return the zero state 
			end if; 
		end if; 

	end if; 

count_out <= temporal_count; 							-- Output 

end process; 										-- End Process 


end Behavioral; 									-- End module.