-- VHDL Test Bench Created from source file counter.vhd -- 17:11:00 07/09/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT counter
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;
		pause : IN std_logic;          
		count_out : OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

	SIGNAL clk :  std_logic;
	SIGNAL reset :  std_logic;
	SIGNAL pause :  std_logic;
	SIGNAL count_out :  std_logic_vector(3 downto 0);
	
	constant CLK_PERIOD : time := 20 ns;
	


BEGIN

	uut: counter PORT MAP(
		clk => clk,
		reset => reset,
		pause => pause,
		count_out => count_out
	);


-- *** Test Bench - User Defined Section ***
   clk_signal : PROCESS
   BEGIN
   clk <= '0';
   	wait for CLK_PERIOD;
   clk <= '1';
   	wait for CLK_PERIOD;
   END PROCESS;

   reset_signal : process
   BEGIN
   reset <= '??';
   	wait for ??;
   reset <= '0';
	wait for ??;
   END PROCESS;

   pause_signal : process
   BEGIN



   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;