LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

--Declaration of ModelSim libraries used
LIBRARY UNISIM;
LIBRARY XILINXCORELIB;


ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS

COMPONENT subtraction
PORT ( 
	BROW_IN 	: in STD_LOGIC;
	XY_IN 	: in STD_LOGIC_VECTOR (1 downto 0);
	BROW_OUT 	: out STD_LOGIC;
	DIFF_OUT 	: out STD_LOGIC
);



END COMPONENT;

SIGNAL br_in : std_logic;
SIGNAL xy_in : std_logic_vector (1 downto 0);
SIGNAL br_out : std_logic;
SIGNAL dif_out : std_logic;

--Defining the variable "CLK_PERIOD" to be
--equal to 50 nano seconds
constant CLK_PERIOD : time:= 50 ns;

BEGIN
--Unit under test is the module subtraction. Notice
--that it is not case sensitive
UUT : subtraction
--Defining external interface signals. This 
--associates ports of the named entity with
--signals in the current architecture.
PORT MAP (
	BROW_IN => br_in,
	XY_IN => xy_in,
	BROW_OUT => br_out,
	DIFF_OUT => dif_out
);


TEST: process
begin

xy_in <= "00"; br_in <= '0';
	wait for CLK_PERIOD;
xy_in <= "00"; br_in <= '1';
	wait for CLK_PERIOD;
xy_in <= "01"; br_in <= '0';
	wait for CLK_PERIOD;
xy_in <= "01"; br_in <= '1';
	wait for CLK_PERIOD;
xy_in <= "10"; br_in <= '0';
	wait for CLK_PERIOD;
xy_in <= "10"; br_in <= '1';
	wait for CLK_PERIOD;
xy_in <= "11"; br_in <= '0';
	wait for CLK_PERIOD;
xy_in <= "11"; br_in <= '1';
	wait for CLK_PERIOD;
end process;

END testbench_arch;