-----------------------------------------------------------------------------------
-- Multiplexor 4-to-1
-----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mux4x1 IS	
	PORT
		(
			S			: IN STD_LOGIC_VECTOR(1 DOWNTO 0);	-- selector
			D0,D1,D2,D3 : IN STD_LOGIC;						-- inputs
			Y			: OUT STD_LOGIC						-- output
		);
END mux4x1;

ARCHITECTURE multiplexor4x1 OF mux4x1 IS

BEGIN

    PROCESS(S, D0, D1, D2, D3)
    BEGIN
		CASE S IS
			WHEN "00" 	=> 		Y <= D0;
			WHEN "01" 	=> 		Y <= D1;
			WHEN "10" 	=> 		Y <= D2;
			WHEN OTHERS => 		Y <= D3;
		END CASE;
	END PROCESS;			
END multiplexor4x1;