--***********************************************************
-- File:		Top counter system file
--		
-- Created:	07/06/2004 AV
--***********************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_counter is
    Port ( clk : in std_logic;
           reset : in std_logic;
           pause : in std_logic;
           anodes : out std_logic_vector(6 downto 0);
           cat1 : out std_logic;
           cat2 : out std_logic);
end top_counter;

architecture structural of top_counter is

--*****************************************************
-- Components declarations -- 
--*****************************************************

	COMPONENT counter
	PORT(
		??
		);
	END COMPONENT;


	COMPONENT disp_controller
	PORT(
		??
		);
	END COMPONENT;

--*****************************************************
-- Signals declarations -- 
--*****************************************************

begin

--*****************************************************
-- Components Instantiations -- 
--*****************************************************

	Inst_counter: counter PORT MAP(
		clk => ??,
		reset => ??,
		pause => ??,
		count_out => ??
	);

	Inst_disp_controller: disp_controller PORT MAP(
		msd => ??,
		lsd => "0000",  -- setting to zero the least significant digit
		clk => ??,
		anodes => ??,
		cat1 => ??,
		cat2 => ??
	);


end structural;

-- The format to complete instantiations is as follow:
-- name_of_component_input/output => name_of_wire(signal)_to_connect_to,
-- Where:
-- name_of_component_input/output is the name of one of the component's port
-- and
-- name_of_wire(signal)_to_connect_to is the name of whatever goes connected
-- to the component in that port. Note that it can be the same as 
-- name_of_component_input/output or it can be a signal (a wire in the system)
-- Note that if you use a signal you will need to declare it !!!