library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock_buffer is
port	(
		clk	:	in	std_logic;
		btn	:	in	std_logic;
		clk_o	:	out	std_logic
		);
end clock_buffer;

architecture behavioral of clock_buffer is


type states is (one,two);
signal state   : states;
signal stop_i  : std_logic := '0';
signal run_i   :std_logic;
signal count_i :std_logic_vector(23 downto 0);


begin

	machine:
	process (clk)
	begin

		if clk'event and clk='1' then
			case state is 
				when one =>	if (btn = '1' and stop_i = '0') then
									state <= two;
									clk_o <= '0';
									run_i <= '1';
								else
									state <= one;
									clk_o <= '0';
									run_i <= '0';
								end if;
							
				when two =>	if stop_i = '1'  then
									state <= one;
									clk_o <= '1';
									run_i <= '0';
								else
									state <= two;
									clk_o <= '0';
									run_i <= '1';
								end if;	    
				when others => clk_o <= '0';
									run_i <= '0';
									state <= one;
			end case;	
		end if;						
	end process machine;

	counter_i:
	process(clk,run_i)
	begin
		if run_i = '1'	then
			if clk'event and clk = '1' then
				if count_i = "111111111111111111111111" then
					stop_i <= '1';
				else 
					stop_i <= '0';
				end if;
				count_i <= count_i + 1;
			end if;
		else 
			count_i <= "000000000000000000000000";
		end if;
	end process counter_i;



end behavioral;