library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity disp_controller is
    Port ( dig_in1 	: in std_logic_vector(3 downto 0);
           dig_in2 	: in std_logic_vector(3 downto 0);
           dig_in3 	: in std_logic_vector(3 downto 0);
           dig_in4 	: in std_logic_vector(3 downto 0);
           clk 	  	: in std_logic;
           cathodes 	: out std_logic_vector(6 downto 0);
           anodes 	: out std_logic_vector(3 downto 0));
end disp_controller;

architecture Behavioral of disp_controller is

signal temp_count 		: std_logic_vector(1 downto 0) := "00";
signal temp 			: std_logic_vector(7 downto 0) := "00000000";
signal fake_clock 		:std_logic;
signal digit_to_display : std_logic_vector(3 downto 0);


begin

fake_clock_process : process (clk, temp(7))
-- This process will slow down the original clk
begin
	if (clk'Event and clk ='1') then
		temp <= temp + 1;
	end if;	
	fake_clock <= temp(7); -- was 7
end process;

count_process : process (fake_clock)
-- This process will take the fake clock and 
-- generate a count to control the anodes
begin
	if (fake_clock'Event and fake_clock ='1') then
		temp_count <= temp_count + 1;
	end if;
end process;

anodes_control : process ( temp_count, dig_in1, dig_in2, dig_in3, dig_in4)
-- This process is taking the count generated in the count_process
-- and generate the output to control the anodes
begin
	case temp_count is
		when "00" => anodes <= "1110";
		   			digit_to_display <= dig_in1;
		when "01" => anodes <= "1101";
		   			digit_to_display <= dig_in2;
		when "10" => anodes <= "1011";
		   			digit_to_display <= dig_in3;
		when "11" => anodes <= "0111";
		   			digit_to_display <= dig_in4;
		when others => anodes <= "0000";
		   			digit_to_display <= dig_in1;
	end case;
end process;

dig_to_sseven_segment: process (digit_to_display)
begin
-- This process is translating the received digit
-- into 7-segment display cathodes inputs
case digit_to_display is

	   when "0000" => cathodes <= "1000000";
	   when "0001" => cathodes <= "1111001";
	   when "0010"	=> cathodes <= "0100100";
	   when "0011" => cathodes <= "0110000";
	   when "0100" => cathodes <= "0011001";
	   when "0101" => cathodes <= "0010010";
	   when "0110" => cathodes <= "0000010";
	   when "0111" => cathodes <= "1111000";
	   when "1000" => cathodes <= "0000000";
	   when "1001" => cathodes <= "0010000";
	   when "1010" => cathodes <= "0001000";
	   when "1011"	=> cathodes <= "0000011";
	   when "1100" => cathodes <= "1000110";
	   when "1101" => cathodes <= "0100001";
	   when "1110" => cathodes <= "0000110";
	   when "1111" => cathodes <= "0001110";
	   when others => cathodes <= "1111111";
end case;
end process;

end Behavioral;