-- VHDL Test Bench Created from source file accumulator.vhd -- 19:31:08 07/20/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench_accum IS
END testbench_accum;

ARCHITECTURE behavior OF testbench_accum IS 

	COMPONENT accumulator
	PORT(
		data_in : IN std_logic_vector(3 downto 0);
		reset : IN std_logic;
		user_set : IN std_logic;          
		sum_out : OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

	SIGNAL data_in :  std_logic_vector(3 downto 0);
	SIGNAL reset :  std_logic;
	SIGNAL user_set :  std_logic;
	SIGNAL sum_out :  std_logic_vector(3 downto 0);
	constant clk_period : time := 20 ns;
BEGIN

	uut: accumulator PORT MAP(
		data_in => data_in,
		reset => reset,
		user_set => user_set,
		sum_out => sum_out
	);


-- *** Test Bench - User Defined Section ***
   reset_signal : PROCESS
   BEGIN
   	reset <= '1';
		wait for 10*clk_period;
		reset <= '0';
		wait for 100*clk_period;
   END PROCESS;

	user_set_signal : process
	begin
		user_set <= '0';
		wait for clk_period;
		user_set <= '1';
		wait for clk_period;
	end process;

	data_in_signal : process
	begin
		data_in <= "0010"	;
		wait for 500*clk_period;
	end process;
-- *** End Test Bench - User Defined Section ***

END;