--VHDL files contain three parts: library declarations, entity and
--behavior.  The library describes what each function will do.  Entity
--describes the inputs and outputs.  Behavior is the working 
--portion of the project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Declaration of the module's inputs and outputs for part 1 of tutorial 2
entity tut1 is port (

A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
Y: out std_logic

); 
end tut1;

--Defining the modules behavior
Architecture behavioral of tut1 is 
begin
process (A,B,C,D) begin 

Y <= (NOT(A) AND B) OR (C AND D);

end process;
end behavioral;