--This is a VHDL testbench.  It is used to stimulate the inputs to 
--file we are testing.  A good design practice is to create a testbench
--for each component you are developing.  Test each component separately
--before combining them.  

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS

COMPONENT tut1
PORT (
A 	: in std_logic;
B 	: in std_logic;
C 	: in std_logic;
D 	: in std_logic;
Y 	: out std_logic
);
END COMPONENT;

--develop signals to stimulate
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL C : std_logic := '0';
SIGNAL D : std_logic := '0';
SIGNAL Y : std_logic := '0';

--UUT means unit under test
BEGIN
UUT : tut1

--map signals on right to entitys on the left
PORT MAP (
A => A,
B => B,
C => C,
D => D,
Y => Y
);
  
signal_A: process
begin
A <= NOT A;
wait for 1 ns;
end process;

signal_B: process
begin
B <= NOT B;
wait for 2 ns;
end process;

signal_C: process
begin
C <= NOT C;
wait for 4 ns;
end process;

signal_D: process
begin
D <= NOT D;
wait for 8 ns;
end process;

END testbench_arch;