Spartan-3E Starter Kit Board User Guide
Lab 1 (01/21/08 - 01/26/08): Introduction to Discrete Digital Logic
Lab 2 (02/04/08 - 02/9/08): Introduction to VHDL, ISE and ModelSim
- Lecture Notes
- Laboratory Manual/Tutorial
- Worksheet
- Lecture notes - slides
- Laboratory files: Source file , Testbench file and Ucf file
Lab 3 (02/11/08 - 02/16/08): Basic VHDL language constructs. Concurrent signal assignment statements, components
- Laboratory Manual/Tutorial
- Worksheet
- Lecture notes - slides
- Laboratory files: Source files
Lab 4 (02/18/08 - 02/23/08): Sequential statements of VHDL. Process. Use of variables in sequential circuit description. Counters
- Laboratory Manual/Tutorial
- Worksheet
- Lecture notes - slides
- Laboratory files: The source code is at the end of the Tutorial
Lab 5 (02/25/08 - 03/01/08): IP Cores
Lab 6 (03/03/08 - 03/15/08): State machines
Lab 7 (03/24/08 - 04/05/08): Two-function calculator
Lab 8 (04/07/08 - 04/12/08): Finite/Algorithmic State Machines
Lab 9 (04/14/08 - 04/26/08): Design of digital circuits using Register Transfer Methodology
- Laboratory Manual/Worksheet
- Lecture notes - slides
- NOTE1: For further information about RTM, please refer to Chapter 11 of the RTL book.
- NOTE2: If you did not turn in Labs 7 and 8 yet, you must turn in them by Wednesday, April 16.
During these two last weeks (04/27/08 - 05/09/08), we'll focus on the final project only (no more lab sessions), which is due May 9. However, the TAs will be available during lab hours to help you with the final project.
