Spartan-3E Starter Kit Board User Guide
How to install Xilinx's software
Lab 1 (06/16/08 - 06/21/08): Introduction to Discrete Digital Logic
Lab 2 (06/23/08 - 06/28/08): Part 1: Introduction to VHDL, ISE and ModelSim; Part 2: Basic VHDL language constructs. Concurrent signal assignment statements, components. READ RTL BOOK SECTION 2, UP TO SUBSECTION 2.2 (included), and SECTION 3, UP TO SUBSECTION 3.2.3 (included)
- Lab Manual Part 1/Tutorial
- Files for part 1: Source file , Testbench file and Ucf file
- Lab Manual Part 2/Tutorial
- Lecture notes - slides
- Worksheet
Lab 3 (06/30/08 - 07/05/08): Sequential statements of VHDL. Process. Use of variables in sequential circuit description. Counters. READ RTL BOOK SUBSECTIONS 3.3 AND 3.5, SECTION 4 UP TO SUBSECTION 4.4 (included), SECTION 5 UP TO SUBSECTION 5.5 (included)
- Laboratory Manual/Tutorial
- Worksheet
- Lecture notes - slides
- Laboratory files: The source code is at the end of the Tutorial
Lab 4 (07/07/08 - 07/12/08): State machines
Lab 5 (07/14/08 - 07/19/08): Finite/Algorithmic State Machines. Please read Sections 10.1 and 10.2
Lab 6 (07/21/08 - 07/26/08): Design of digital circuits using Register Transfer Methodology
